ST7MC1K2 datasheet(99/371 Pages) STMICROELECTRONICS

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On-chip peripherals

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Table 38.

ARTCSR register description

Bit

Name

Function

EXCL

External clock

This bit is set and cleared by software. It selects the input clock for the 7-bit

prescaler.

0: CPU clock

1: External clock

6:4 CC[2:0]

Counter clock control

These bits are set and cleared by software. They determine the prescaler division

ratio from fINPUT:

000: Prescaler division ratio from fINPUT =fINPUT (fCOUNTER)

and 8 MHz (with fINPUT =8 MHz)

001: Prescaler division ratio from fINPUT =fINPUT/2 (fCOUNTER)

and 4 MHz (with fINPUT =8 MHz)

010: Prescaler division ratio from fINPUT =fINPUT/4 (fCOUNTER)

and 2 MHz (with fINPUT =8 MHz)

011: Prescaler division ratio from fINPUT =fINPUT/8 (fCOUNTER)

and 1 MHz (with fINPUT =8 MHz)

100: Prescaler division ratio from fINPUT =fINPUT/16 (fCOUNTER)

and 500 kHz (with fINPUT =8 MHz)

101: Prescaler division ratio from fINPUT =fINPUT/32 (fCOUNTER)

and 250 kHz (with fINPUT =8 MHz)

110: Prescaler division ratio from fINPUT =fINPUT/64 (fCOUNTER)

and 125 kHz (with fINPUT =8 MHz)

111: Prescaler division ratio from fINPUT =fINPUT/128 (fCOUNTER)

and 62.5 kHz (with fINPUT =8 MHz)

3TCE

Timer counter enable

This bit is set and cleared by software. It puts the timer in the lowest power

consumption mode.

0: Counter stopped (prescaler and counter frozen)

1: Counter running

FCRL

Force counter reload

This bit is write-only and any attempt to read it yields a logical zero. When set, it

causes the contents of ARTARR register to be loaded into the counter, and the

content of the prescaler register to be cleared in order to initialize the timer before

starting to count.

1OIE

Overflow interrupt enable

This bit is set and cleared by software. It allows to enable/disable the interrupt which

is generated when the OVF bit (bit 0) is set.

0: Overflow interrupt disable

1: Overflow interrupt enable

0OVF

Overflow flag

This bit is set by hardware and cleared by software reading the ARTCSR register. It

indicates the transition of the counter from FFh to the ARTARR value.

0: New transition not yet reached

1: Transition reached

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