ST7MC1K2 datasheet(51/371 Pages) STMICROELECTRONICS

51 / 371 page

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6.5.4

Low power modes

Interrupts

The CSS or AVD interrupt events generate an interrupt if the corresponding enable control

bit (CSSIE or AVDIE) is set and the interrupt mask in the CC register is reset (RIM

instruction).

6.5.5

System integrity control/status register (SICSR, page 0)

Table 7.

Effect of low power modes on SI

Mode

Description

Wait

No effect on SI. CSS and AVD interrupts cause the device to exit from Wait mode.

Halt

The CRSR register is frozen.

The CSS (including the safe oscillator) is disabled until Halt mode is exited. The previous

CSS configuration resumes when the MCU is woken up by an interrupt with ‘exit from Halt

mode’ capability or from the counter reset value when the MCU is woken up by a RESET.

The AVD remains active, and an AVD interrupt can be used to exit from Halt mode.

Table 8.

SI interrupt control/wake-up capability

Interrupt event

Event flag

Enable control

bit

Exit from

WAIT

Exit from

HALT

CSS event detection

(safe oscillator activated as main clock)

CSSD

CSSIE

Yes

No(1)

This interrupt allows to exit from Active Halt mode.

AVD event

AVDF

AVDIE

Yes

SICSR, page 0

Reset value: 000x 000x (00h)

654

PAGE

AVDIE

AVDF

LVDRF

Reserved

CSSIE

CSSD

WDGRF

R/W

Table 9.

SICSR (page 0) register description

Bit

Name

Function

7PAGE

SICSR register page selection

This bit selects the SICSR register page. It is set and cleared by software;

0: Access to SICSR register mapped in page 0

1: Access to SICSR register mapped in page 1

6AVDIE

Voltage detector interrupt enable

This bit is set and cleared by software. It enables an interrupt to be generated when

the AVDF flag changes (toggles). The pending interrupt information is automatically

cleared when software enters the AVD interrupt routine.

0: AVD interrupt disabled

1: AVD interrupt enabled

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