ST7MC1K2 datasheet(56/371 Pages) STMICROELECTRONICS

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6.6.6

Interrupts

The MCC/RTC interrupt event generates an interrupt if the OIE bit of the MCCSR register is

set and the interrupt mask in the CC register is not active (RIM instruction).

6.6.7

MCC control status register (MCCSR)

Table 12.

MCC/RTC interrupt control/wake-up capability

Interrupt event

Event flag

Enable control bit Exit from WAIT

Exit from HALT

Time base overflow event

OIF

OIE

Yes

No(1)

The MCC/RTC interrupt wakes up the MCU from Active Halt mode, not from Halt mode.

MCCSR

Reset value: 0000 0000 (00h)

654

MCO

CP[1:0]

SMS

TB[1:0]

OIE

OIF

R/W

Table 13.

MCCSR register description

Bit

Name

Function

MCO

Main clock out selection

This bit enables the MCO alternate function on the PF0 I/O port. It is set and cleared

by software.

0: MCO alternate function disabled (I/O pin free for general-purpose I/O)

1: MCO alternate function enabled (fOSC2on I/O port)

Note: To reduce power consumption, the MCO function is not active in Active Halt

mode.

6:5 CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is applied in the different slow

modes. Their action is conditioned by the setting of the SMS bit. These two bits are

set and cleared by software:

00: fCPU in slow mode = fOSC2/2

01: fCPU in slow mode = fOSC2/4

10: fCPU in slow mode = fOSC2/8

11: fCPU in slow mode = fOSC2/16

4SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU =fOSC2

1: Slow mode. fCPU is given by CP1, CP0

See Section 8.2: Slow mode and Section 6.6: Main clock controller with real time

clock and beeper (MCC/RTC) for more details.

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