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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ST7MC1K2 Arkusz danych(PDF) 108 Page - STMicroelectronics |
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ST7MC1K2 Arkusz danych(HTML) 108 Page - STMicroelectronics |
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108 / 371 page  Obsolete Product(s) - Obsolete Product(s) On-chip peripherals ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto 108/371 A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 42. Counter timing diagram, internal clock divided by 2 Figure 43. Counter timing diagram, internal clock divided by 4 Figure 44. Counter timing diagram, internal clock divided by 8 Note: The device is in reset state when the internal reset signal is high, when it is low the device is running. CPU clock FFFD FFFE FFFF 0000 0001 0002 0003 Internal reset Timer clock Counter register Timer overflow flag (TOF) FFFC FFFD 0000 0001 CPU clock Internal reset Timer clock Counter register Timer overflow flag (TOF) CPU clock Internal reset Timer clock Counter register Timer overflow flag (TOF) FFFC FFFD 0000 Obsolete Product(s) - Obsolete Product(s) |
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