ST7MC1K2 datasheet(123/371 Pages) STMICROELECTRONICS

123 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

123/371

Input capture 1 high register (IC1HR)

This is an 8-bit read-only register that contains the high part of the counter value (transferred

by the input capture 1 event).

Input capture 1 low register (IC1LR)

This is an 8-bit read-only register that contains the low part of the counter value (transferred

by the input capture 1 event).

Output compare 1 high register (OC1HR)

This is an 8-bit register that contains the high part of the value to be compared to the CHR

3OCF2

Output compare flag 2

0: No match (reset value)

1: The content of the free running counter has matched the content of the OC2R

the OC2R (OC2LR) register.

2TIMD

Timer disable

This bit is set and cleared by software. When set, it freezes the timer prescaler and

counter and disabled the output functions (OCMP1 and OCMP2 pins) to reduce

power consumption. Access to the timer registers is still available, allowing the timer

configuration to be changed while it is disabled.

0: Timer enabled

1: Timer prescaler, counter and outputs disabled

1:0

Reserved, must be kept cleared

IC1HR

Reset value: undefined

654

MSB

LSB

IC1LR

Reset value: undefined

654

MSB

LSB

OC1HR

Reset value: 1000 0000 (80h)

654

MSB

LSB

R/W

Table 52.

CSR register description (continued)

Bit Name

Function

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2 Arkusz danych(PDF) 123 Page - STMicroelectronics

ST7MC1K2 Arkusz danych(HTML) 123 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL