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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADBMS2950BCCSZ Arkusz danych(PDF) 29 Page - Analog Devices |
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ADBMS2950BCCSZ Arkusz danych(HTML) 29 Page - Analog Devices |
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29 / 97 page  Data Sheet ADBMS2950B Rev. 0 | Page 29 of 97 commands allow to read from the first device in the chain only. The Read (RD48) commands allow to access data from all devices in the chain. The following example assumes two ADBMS2950B (NP = 2) and five ADBMS6830B (NQ = 5) making a total of seven devices in the daisy-chain. Table 37. Daisy Chain Command Types Type Bc Bd B Description A 4 0 4 Action command, no data bytes. R1 4 8 12 Read from 1st device in daisy-chain (Bd = 8). W1 4 8 12 Write to 1st device in daisy-chain (Bd = 8). RP 4 16 20 Read from pack monitors (first in chain) only (Bd = NP × 8). WP 4 16 20 Write to pack monitors (first in chain) only (Bd = NP × 8). RALL 4 20 24 Read All from 1st device in daisy-chain (Bd = 20). R 4 56 60 Read from all devices in daisy-chain (Bd = N × 8). W 4 56 60 Write to all devices in daisy-chain (Bd = N × 8). Table 38 shows the timing of an example sequence, triggering cell voltage and battery pack voltage and current conversions, read all cells from all cell monitors and read voltages and currents from all pack monitors. Note that the ADI1 and ADCV are compatible commands. When sending ADCV to a daisy-chain, all cell monitor devices trigger cell conversion and all pack monitor devices trigger pack current and voltage conversion synchronously. In result, it is not required to send ADCV and ADI1 separately. Also, in typical applications, ADCV or ADI1 are issued with the CONT bit set only once after initialization, resulting in the related ADCs to operate continuously. The conversion result registers update periodically and can be read by the host controller any time. The SNAP, UNSNAP commands allow to read data coherently from the daisy-chain. Table 38. Daisy-Chain Pack and Cell Monitor Sequence Example # CMD Type B T Description 1 ADCV, ADI1 A 4 18 μs Trigger cell voltage and current conversion. 2 ADV A 4 18 μs Trigger VxADCs. 3 RDACA R 60 242 μs Read cells 1 to 3. 4 RDACB R 60 242 μs Read cells 4 to 6. 5 RDACC R 60 242 μs Read cells 7 to 9. 6 RDACD R 60 242 μs Read cells 10 to 12. 7 RDACE R 60 242 μs Read cells 13 to 15. 8 RDACF R 60 242 μs Read cells 16. 9 RDV1A RP 20 82 μs Read V1ADC results V1A to V3A. 10 RDV1B RP 20 82 μs Read V1ADC results V4A to V6A. 11 RDV1C RP 20 82 μs Read V1ADC results V7A, V8A, VREF2A. 12 RDIACC RP 20 82 μs Read battery pack current. 13 RDVBACC RP 20 82 μs Read battery pack voltage. # CMD Type B T Description Total 468 1.9 ms CORE STATE DESCRIPTION Figure 27. Core State Diagram Power-Down State The ADBMS2950B is in power-down state when its VDD and VREG supplies are not provided. In this state, the OCx, GPIO, and GPO output pins as well as the V1 to V10 and VBAT input pins are high impedance. External sources can charge the VREG pin through conductive paths of internal protection diodes as shown in the ESD protection diagram (see Figure 50). In turn, VREG can charge VDD through another internal protection diode. The total current that is injected into VREG in this manner should not exceed 4 mA. Once VREG has reached its power-on reset threshold (see Table 13), the IC transition to the STANDBY state (as shown in STANDBY State) after tWAKE, and subsequently transition to the REFUP state (as shown in REFUP State). Because of the internal protection diode, the VDD pin voltage minimum tracks the VREG pin voltage minus the diode forward voltage (~0.6V). The VDD pin must not be forced externally more than 0.3V below VREG (see Table 18). STANDBY State In the STANDBY state, the internal oscillators and references are activated, and the host can communicate with the IC. When VDD is above 11V, the DRIVE pin is driven to ~5.7V. Once the references are guaranteed to meet their specified inaccuracy (after tREFUP), the IC automatically transitions to the REFUP State. To distinguish the STANDBY state from the REFUP State, the bit REFUP in CFGA register (see Table 69) can be read. ADC measurements cannot be initiated in the STANDBY state but only in the REFUP State. If the host sends an ADC command (ADI1, ADI2, ADV, and ADX), the IC acknowledges it through incrementing the command counter, but the ADCs are not triggered. Instead, the host should either wait for the maximum tREFUP or for the REFUP bit set to 1. |
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