ADBMS2950BCCSZ datasheet(45/97 Pages) AD

45 / 97 page

Data Sheet

ADBMS2950B

Rev. 0 | Page 45 of 97

In both the PWM modes, the OCA and OCB pins output a

non-latched version of the majority decision. When the

overcurrent condition disappears at the input of the device, it

also disappears again at the output, after a latency depending on

the OCDGT setting. However, when configured in static mode,

the OCA and OCB pins output the state of the OCAL and

OCBL latches. One needs to manually clear the latched OCAL

and OCBL bits with the CLRFLAG command to de-assert the

static outputs.

Static Overcurrent Output Mode

In the static overcurrent output mode, the OCA and OCB pins

are either static de-asserted, in case of no overcurrent, or static

asserted and latched in case of an overcurrent event that passed

the deglitch filter.

PWM Overcurrent Output Modes

The two PWM overcurrent output modes, with the coding as

shown in Figure 37, can be selected through OCMODE. The

frequency of the PWM is equal to the conversion rate of the

OCxADC which is 16 kHz. All the ADCs operate from the

same global clock with tolerance of 10%. Therefore, the ADC

conversion rates and the PWM frequency have the same

tolerance. The duty cycle is clock accurate and only varies with

the signal slew rate and threshold on the receiver side. The duty

cycle steps (12.5% for PWM1 and 25% for PWM2) give enough

headroom for such variations.

Figure 37. PWM1 and PWM2 Coding

PWM1 Overcurrent Output Mode

The PWM1 mode is optimized for the direct communication of

overcurrent events to pyrofuse ignition hardware. The latter is

assumed to be designed in such a way that it triggers the

pyrofuse ignition only if two or more PWM output periods

have a 75% duty cycle. The OCA and OCB pins output a 75%

duty cycle when the majority voters assert overcurrent while

neither a fault nor a diagnostic cycle is pending in the device.

When there is no overcurrent, the OCA and OCB pins output a

25% duty cycle. While diagnostics are ongoing or faults are

pending, the OCA and OCB pins output a 0% duty cycle. This

can trigger an external timeout detector.

The given duty cycles are for the non-inverted output selected

by OCAX = 0, OCBX = 0. When these bits are set to 1 instead,

the duty cycle of the respective outputs are essentially inverted,

leading to (100% − non-inverted duty cycle) 75% is changed to

25% and 0% is changed to 100%.

To prevent unintended ignition because of a fault that causes

the OSC1 clock to stop during the active time of the duty cycle,

the active state of the duty cycle is gated by the output signal

from the no-clock detection.

The external circuit can further deglitch events for more

conservative ignition because the overcurrent events are not

latched inside the IC.

Table 60. PWM1 Overcurrent Output Mode Duty-Cycle Coding for OCAX = 0, OCBX = 0

Duty Cycle

Description

0% - High-Z

OCx pins in high impedance state after reset and whenever OCEN = 0.

0% - Active-low

OCx pins actively driven low. Detection of any SPF which is a DFI for OC1-2-3 or when executing diagnostic for OC.

25%

OC threshold is not violated by more than one OCxADC (no overcurrent).

75%

OC threshold is violated by more than one OCxADC.

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