ADBMS2950BCCSZ datasheet(92/97 Pages) AD

92 / 97 page

ADBMS2950B

Data Sheet

Rev. 0 | Page 92 of 97

possible to calculate a moving average for all channels in the

described fashion. Note that, at higher frequencies, the filter

response is limited by the RC filter and the response of the

VxADC due to its non-continuous operation.

Figure 81. VxADC with Average Filter Transfer Function

CONTINUOUS SAMPLING AND COULOMB

COUNTING

The precise current measurement ADCs of the ADBMS2950B

can be used to perform coulomb counting, which is often used

to calculate the state-of-charge of the battery. To measure the

charge that is flowing into or out of the battery precisely, a user

requires:

•

Lossless and continuous sampling of the current sense

input.

•

Equal sample weighting and true average

measurement.

•

Precise time measurement to integrate the current

measurements into charge.

The ADBMS2950B provides all functionalities to fulfill those

requirements. The first order delta-sigma ADCs have an over-

sampling rate of 4.1 MHz, can run continuously on the current

(and VBAT) channels, and weigh all samples equally providing

the exact average of the input signal over the conversion

window, which is either 1 ms (Ix registers) or ACCN × 1 ms

(IxACC registers – also see ACCI configuration).

The host controller can decide to either read the Ix or the

IxACC registers continuously depending on the current

measurement period requirement.

In both cases, there is no loss of sampling time (no holes) on the

inputs. The host controller can synchronize to the continuously

updated conversion result registers by reading the conversion

(phase) counter I1CNT, I1PHA.

The I1CNT register increments by one with every 1 ms

conversion result. Assuming an ACCN setting of 8 (ACCI = 1),

with the 8th of those 1 ms conversion results, the accumulated

registers (IxACC) are updated with the sum of 8 conversions.

Consequently, this happens every time the I1CNT value reports

a multiple of 8.

The conversion phase counter I1PHA provides additional

resolution by adding 4 sub-counts per I1CNT count. If the

I1CNT, I1PHA counters are treated as a single counter

(I1CNTPHA[12:0]), the 1 ms conversion results are updated

every time the host reads 0, 4, 8, 12, …. and the 8 ms

accumulated conversion results (assuming ACCI = 1) are

updated every time the host reads 0, 32, 64, 96, … For any value

in between, the conversion result register is not updated, giving

the host enough time to read the results. The snap and unsnap

commands ensure coherent reading of the I1CNTPHA and Ix

(or IxACC) registers retrieved via separate read commands.

Lossless Continuous Conversion Reading

This chapter shows a procedure to read every 8 ms accumulated

conversion (IxACC update rate for ACCN = 8) without missing

any result. Not to miss any conversion, the host must read at a

period that is shorter than the shortest possible update rate of

the IxACC registers, which occurs at the maximum specified IC

oscillator frequency. The oscillator frequency of the

ADBMS2950B is specified to be within ±10% over the full-

operating temperature range. Consequently, the host must read

every 7.2 ms or faster (the IxACC registers are updated

nominally every 8 ms for ACCN = 8).

Table 89 shows the timings of the I1CNT and number of

IxACC conversions (CntACC) acquired, assuming a host reads

every 7 ms. The values I1CNT and CntACC are shown for a

device running at minimum (MIN), nominal (NOM), and

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