ATmega325P datasheet(77/364 Pages) ATMEL

77 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

Note:

1. AIN0D and AIN1D is described in ”DIDR1 – Digital Input Disable Register 1” on page 205.

13.3.4

Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 13-11. If

some Port F pins are configured as outputs, it is essential that these do not switch when a con-

version is in progress. This might corrupt the result of the conversion. If the JTAG interface is

enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even

if a reset occurs.

• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7.

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Reg-

ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

Table 13-10. Overriding Signals for Alternate Functions in PE3:PE0

Signal Name

PE3/AIN1/

PCINT3

PE2/XCK/AIN0/

PCINT2

PE1/TXD/

PCINT1

PE0/RXD/

PCINT0

PUOE

XCK OUTPUT

ENABLE

TXEN

RXEN

PUOV

0XCK

0PORTE0 • PUD

DDOE

TXEN

RXEN

DDOV

0010

PVOE

TXEN

PVOV

TXD

PTOE

––––

DIEOE

(PCINT3 • PCIE0)

+ AIN1D(1)

(PCINT2 • PCIE0)

+ AIN0D(1)

PCINT1 • PCIE0

PCINT0 • PCIE0

DIEOV

PCINT3 • PCIE0

PCINT2 • PCIE0

PCINT3 INPUT

XCK/PCINT2

INPUT

PCINT1 INPUT

RXD/PCINT0

INPUT

AIO

AIN1 INPUT

AIN0 INPUT

–

Table 13-11. Port F Pins Alternate Functions

Port Pin

Alternate Function

PF7

ADC7/TDI (ADC input channel 7 or JTAG Test Data Input)

PF6

ADC6/TDO (ADC input channel 6 or JTAG Test Data Output)

PF5

ADC5/TMS (ADC input channel 5 or JTAG Test mode Select)

PF4

ADC4/TCK (ADC input channel 4 or JTAG Test ClocK)

PF3

ADC3 (ADC input channel 3)

PF2

ADC2 (ADC input channel 2)

PF1

ADC1 (ADC input channel 1)

PF0

ADC0 (ADC input channel 0)

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