ATmega325P datasheet(40/364 Pages) ATMEL

40 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

9.6

Power-down Mode

When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the

USI start condition detection, and the Watchdog continue operating (if enabled). Only an Exter-

nal Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level

interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically

halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed

level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 58

for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs

until the wake-up becomes effective. This allows the clock to restart and become stable after

having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the

Reset Time-out period, as described in ”Clock Sources” on page 30.

9.7

Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Power-

save mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from

either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding

Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in

SREG is set.

If Timer/Counter2 is running, Power-down mode is recommended instead of Power-save mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save

mode. The clock source for the two modules can be selected independent of each other. If the

Timer/Counter2 is using the asynchronous clock, the Timer/Counter Oscillator is stopped during

sleep. If the Timer/Counter2 is using the synchronous clock, the clock source is stopped during

sleep. Note that even if the synchronous clock is running in Power-save, this clock is only avail-

able for the Timer/Counter2.

9.8

Standby Mode

When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the

SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down

with the exception that the Oscillator is kept running. From Standby mode, the device wakes up

in six clock cycles.

9.9

Power Reduction Register

The Power Reduction Register (PRR), see ”PRR – Power Reduction Register” on page 44, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers inaccessible. Resources used by

the peripheral when stopping the clock will remain occupied so the peripheral should be disabled

before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts

the module in the same state as before shutdown.

Module shutdown can be used in IDLE mode and active mode to reduce the overall power con-

sumption. In all other sleep modes, the clock is already stopped.

ATmega325P Arkusz danych(PDF) 40 Page - ATMEL Corporation

ATmega325P Arkusz danych(HTML) 40 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Arkusz danych Pobierz

Link URL