| Zakładka z wyszukiwarką danych komponentów |
|
ATmega325P Arkusz danych(PDF) 96 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATmega325P Arkusz danych(HTML) 96 Page - ATMEL Corporation |
|
96 / 364 page ![]() 96 8023F–AVR–07/09 ATmega325P/3250P the pin is set to output. The waveform generated will have a maximum frequency of f OC0 = f clk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following equation: The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 14.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 14-6. Fast PWM Mode, Timing Diagram The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. fOCnx f clk_I/O 2 N 1 OCRnx + () ⋅⋅ -------------------------------------------------- = TCNTn OCRnx Update and TOVn Interrupt Flag Set 1 Period 2 3 OCn OCn (COMnx1:0 = 2) (COMnx1:0 = 3) OCRnx Interrupt Flag Set 4 5 6 7 |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |