ATmega325P datasheet(21/364 Pages) ATMEL

21 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

these addressing modes. The Register File is described in ”General Purpose Register File” on

page 14.

Figure 7-2.

Data Memory Map

7.3.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 7-3.

Figure 7-3.

On-chip Data SRAM Access Cycles

7.4

EEPROM Data Memory

The ATmega325P/3250P contains 1K bytes of data EEPROM memory. It is organized as a sep-

arate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 285, page 291, and page 274 respectively.

7.4.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

32 Registers

64 I/O Registers

Internal SRAM

(2048 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x08FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

0x0100

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

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