ATmega325P datasheet(42/364 Pages) ATMEL

42 / 364 page

8023F–AVR–07/09

ATmega325P/3250P

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 67 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or have

an analog signal level close to V

CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and

DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 205 and ”DIDR0 – Digital

Input Disable Register 0” on page 222 for details.

9.10.7

JTAG Interface and On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or

Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will

contribute significantly to the total current consumption. There are three alternative ways to

avoid this:

• Disable OCDEN Fuse.

• Disable JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is

not shifting data. If the hardware connected to the TDO pin does not pull up the logic level,

power consumption will increase. Note that the TDI pin for the next device in the scan chain con-

tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or

leaving the JTAG fuse unprogrammed disables the JTAG interface.

ATmega325P Arkusz danych(PDF) 42 Page - ATMEL Corporation