ATmega325P datasheet(93/364 Pages) ATMEL

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8023F–AVR–07/09

ATmega325P/3250P

14.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the

OCF0A Flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare

match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or

toggled).

14.5.2

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

14.5.3

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock

cycle, there are risks involved when changing TCNT0 when using the Output Compare unit,

independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

counting down.

The setup of the OC0A should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-

pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when

changing between Waveform Generation modes.

Be aware that the COM0A1:0 bits are not double buffered together with the compare value.

Changing the COM0A1:0 bits will take effect immediately.

14.6

Compare Match Output Unit

The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator

uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare

match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 14-4 shows a sim-

plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits,

and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis-

ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the

OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a System

Reset occur, the OC0A Register is reset to “0”.

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