ATmega325P datasheet(44/364 Pages) ATMEL

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8023F–AVR–07/09

ATmega325P/3250P

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed

while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is

automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable

is controlled by a timed sequence.

9.11.3

PRR – Power Reduction Register

• Bits 7:4- Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is

enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to

the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper

operation.

• Bit 1 - PRUSART: Power Reduction USART

Writing logic one to this bit shuts down the USART by stopping the clock to the module. When

waking up the USART again, the USART should be re-initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

The analog comparator cannot use the ADC input MUX when the ADC is shut down.

Note:

The Analog Comparator is disabled using the ACD-bit in the ”ACSR – Analog Comparator Control

and Status Register” on page 204.

Bit

210

(0x64)

–

PRTIM1

PRSPI

PRUSART0

PRADC

PRR

Read/Write

R/W

Initial Value

ATmega325P Arkusz danych(PDF) 44 Page - ATMEL Corporation