MPC5121E datasheet(23/86 Pages) FREESCALE

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Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

3.1.4

Electrostatic Discharge

CAUTION

This device contains circuitry that protects against damage due to high-static voltage or

electrical fields. However, it is advised that normal precautions be taken to avoid

application of any voltages higher than maximum-rated voltages. Operational

reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (GND

or VDD). Table 10 gives package thermal characteristics for this device.

3.1.5

Power Dissipation

Power dissipation of the MPC5121e/MPC5123 is caused by 4 different components: the dissipation of the internal or core

digital logic (supplied by VDD_CORE), the dissipation of the analog circuitry (supplied by SYS_PLL_AVDD and

CORE_PLL_AVDD), the dissipation of the IO logic (supplied by VDD_MEM_IO and VDD_IO) and the dissipation of the PHYs

(supplied by own supplies). Table 9 details typical measured core and analog power dissipation figures for a range of operating

modes. However, the dissipation due to the switching of the IO pins can not be given in general, but must be calculated for each

application case using the following formula:

Eqn. 1

where N is the number of output pins switching in a group M, C is the capacitance per pin, VDD_IO is the IO voltage swing, f

is the switching frequency and PIOint is the power consumed by the unloaded IO stage. The total power consumption of the

device must not exceed the value that would cause the maximum junction temperature to be exceeded.

Eqn. 2

Table 8. ESD and Latch-Up Protection Characteristics

Sym

Rating

Min

Max

Unit

SpecID

VHBM

Human Body Model (HBM) – JEDEC JESD22-A114-B

2000

—

D4.1

VMM

Machine Model (MM) – JEDEC JESD22-A115

200

—

D4.2

VCDM

Charge Device Model (CDM) – JEDEC JESD22-C101

500

—

D4.3

Table 9. Power Dissipation

Core Power Supply (VDD_CORE)

SpecID

Mode

High-Performance

Unit

e300 = 300 MHz, CSB = 200 MHz

Operational1

800

D5.1

Deep-Sleep1

1mW

D5.2

Hibernation

D5.3

PLL/OSC Power Supplies (SYS_PLL_AVDD, CORE_PLL_AVDD)

Typical

D5.4

Unloaded I/O Power Supplies (VDD_IO, VDD_MEM_IO)

IOint

∑

CVDD_IO

total

core

analog

PPHYs

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