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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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MPC5121E Arkusz danych(PDF) 60 Page - Freescale Semiconductor, Inc |
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MPC5121E Arkusz danych(HTML) 60 Page - Freescale Semiconductor, Inc |
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60 / 86 page  MPC5121E/MPC5123 Data Sheet, Rev. 4 Electrical and Thermal Characteristics Freescale Semiconductor 60 Figure 40. SDHC Timing Diagram Table 36 lists the timing parameters. . Table 36. MMC/SD Interface Timing Parameters ID Parameter Symbols Min Max Unit SpecID Card Input Clock SD1 Clock Frequency (Low Speed) fPP 1 1 In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V. 0 400 kHz A14.1 Clock Frequency (SD/SDIO Full Speed/High Speed) fPP 2 2 In normal data transfer mode for SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. 0 25/50 MHz A14.2 Clock Frequency (MMC Full Speed/High Speed) fPP 3 3 In normal data transfer mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. 0 20/52 MHz A14.3 Clock Frequency (Identification Mode) fOD 4 4 In card identification mode, card clock must be 100 kHz ~ 400 kHz, voltage ranges from 2.7 to 3.6 V. 100 400 kHz A14.4 SD2 Clock Low Time (Full Speed/High Speed) tWL 10/7 ns A14.5 SD3 Clock High Time (Full Speed/High Speed) tWH 10/7 ns A14.6 SD4 Clock Rise Time (Full Speed/High Speed) tTLH 10/3 ns A14.7 SD5 Clock Fall Time (Full Speed/High Speed) tTHL 10/3 ns A14.8 SDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD6 SDHC Output Delay tOD TH5 –3 5 Suggested ClockPeriod = T, CLK_DIVIDER (in SDHC Clock Rate Register) = D, then TH = [(D + 1)/2]/(D + 1) × T where the value is rounded. TH+3 ns A14.9 SDHC Input / Card Outputs CMD, DAT (Reference to CLK) SD7 SDHC Input Setup Time tISU 2.5 ns A14.10 SD8 SDHC Input Hold Time tIH 2.5 ns A14.11 SD1 SD3 SD5 SD7 SD4 SD8 MMCx_CMD Output from SDHC to card MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 MMCx_DAT_0 MMCx_CMD Input from card to SDHC MMCx_DAT_1 MMCx_DAT_2 MMCx_DAT_3 MMCx_DAT_0 MMCx_CLK SD2 SD6 |
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