MPC5121E datasheet(36/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

For Measurement and Test Conditions, see the PCI Local Bus Specification.

3.3.7

LPC

The Local Plus Bus is the external bus interface of the MPC5121e/MPC5123. A maximum of eight configurable chip selects

(CS) are provided. There are two main modes of operation: non-MUXed and MUXED. The reference clock is the LPC CLK.

The maximum bus frequency is 83 MHz.

Definition of Acronyms and Terms:

WS = Wait State

DC = Dead Cycle

HC = Hold Cycle

DS = Data Size in Bytes

BBT = Burst Bytes per Transfer

AL = Address latch enable Length

ALT = Chip select/Address Latch Timing

tLPCck = LPC clock period

4 See the timing measurement conditions in the PCI Local Bus Specification.

Table 23. LPC Timing

Sym

Description

Min

Max

Units

SpecID

tOD

CS[x], ADDR, R/W, TSIZ, DATA (wr),

TS, OE valid after LPC CLK

(Output Delay related to LPC CLK)

A7.1

Non-MUXed non-Burst CS[x] pulse

width

(2 +WS) ×tLPCck

A7.2

ADDR, R/W, TSIZ, DATA (wr) valid

before CS[x] assertion

tLPCck –tOD

tLPCck +tOD

A7.3

OE assertion after CS[x] assertion

tLPCck –tOD

tLPCck +tOD

A7.4

ADDR, R/W, TSIZ, Data (wr) hold after

CS[x] negation

tLPCck –tOD

(HC + 1) × tLPCck +tOD

A7.5

TS pulse width

tLPCck

A7.6

DATA (rd) setup before LPC CLK

—

A7.7

DATA (rd) input hold

(DC + 1) × tLPCck

A7.8

Non-MUXed read Burst CS[x] pulse

width

(2 + WS + BBT/DS) × tLPCck (2 + WS + BBT/DS) × tLPCck

A7.9

Burst ACK pulse width

(BBT/DS) × tLPCck

A7.10

t10

Burst DATA (rd) input hold

—

A7.11

t11

Read Burst ACK assertion after CS[x]

assertion

(2 +WS) ×tLPCck

A7.12

t12

Non-muxed write Burst CS[x] pulse

width

(2.5 + WS + BBT/DS) × tLPCck (2.5 + WS + BBT/DS) × tLPCck

A7.13

t13

Write Burst ADDR, R/W, TSIZ, DATA

(wr) hold after CS[x] negation

0.5 × tLPCck –tOD

(HC + 0.5) × tLPCck +tOD

A7.14

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