| Zakładka z wyszukiwarką danych komponentów |
|
MPC5121E Arkusz danych(PDF) 73 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC5121E Arkusz danych(HTML) 73 Page - Freescale Semiconductor, Inc |
|
73 / 86 page ![]() Electrical and Thermal Characteristics MPC5121E/MPC5123 Data Sheet, Rev. 4 Freescale Semiconductor 73 3.3.23 IEEE 1149.1 (JTAG) Figure 53. Timing Diagram – JTAG Clock Input Table 50. JTAG Timing Specification Sym Characteristic Min Max Unit SpecID — TCK frequency of operation 0 25 MHz A23.1 1 TCK cycle time 40 — ns A23.2 2 TCK clock pulse width measured at 1.5V 1.08 — ns A23.3 3 TCK rise and fall times 0 3 ns A23.4 4TRST setup time to tck falling edge1 1 TRST is an asynchronous signal. The setup time is for test purposes only. 10 — ns A23.5 5TRST assert time 5 — ns A23.6 6 Input data setup time2 2 Non-test, other than TDI and TMS, signal input timing with respect to TCK. 5 — ns A23.7 7 Input data hold time2 15 — ns A23.8 8 TCK to output data valid3 3 Non-test, other than TDO, signal output timing with respect to TCK. 0 30 ns A23.9 9 TCK to output high impedance3 030 ns A23.10 10 TMS, TDI data setup time. 5 — ns A23.11 11 TMS, TDI data hold time. 1 — ns A23.12 12 TCK to TDO data valid. 0 15 ns A23.13 13 TCK to TDO high impedance. 0 15 ns A23.14 TCK VM VM VM 3 3 2 2 1 VM = Midpoint Voltage |
|
Link URL |
| Czy Alldatasheet okazała się pomocna? [ DONATE ] |
O Alldatasheet | Reklama | Kontakt | Polityka prywatności | Link do karty katalogowej | Linki | Lista producentów All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |