MPC5121E datasheet(71/86 Pages) FREESCALE

Numer części	MPC5121E

Szczegółowy opis	e300 Power Architecture processor core

PDF	86 Pages

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Producent	FREESCALE [Freescale Semiconductor, Inc]

Strona internetowa	http://www.freescale.com

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Electrical and Thermal Characteristics

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

Figure 51. Timing Diagram – SPI Master Mode, Format 1 (CPHA = 1)

NOTE

Output timing is specified at a nominal 50 pF load.

Table 47. Timing Specifications – SPI Slave Mode, Format 1 (CPHA = 1)

Sym

Description

Min

Max

Units

SpecID

SCK cycle time, programable in the PSC CCS register

30.0

—

A20.56

SCK pulse width, 50% SCK duty cycle

15.0

—

A20.57

Slave select clock delay

0.0

—

A20.58

Output data valid

—

14.0

A20.59

Input Data setup time

2.0

—

A20.60

Input Data hold time

1.0

—

A20.61

Slave disable lag time

0.0

—

A20.62

Minimum Sequential Transfer delay = 2 × IP-Bus clock cycle time

30.0

—

A20.63

SCK

(CLKPOL=0)

SCK

(CLKPOL=1)

MOSI

Output

MISO

Input

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