MPC5121E datasheet(76/86 Pages) FREESCALE

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MPC5121E/MPC5123 Data Sheet, Rev. 4

System Design Information

Freescale Semiconductor

System Design Information

4.1

Power Up/Down Sequencing

Power sequencing between the 1.4 V power supply VDD_CORE and the remaing supplies is required to prevent excessive current

during power up phase.

The required power sequence is as follows:

•

Use 12 V/millisecond or slower time for all supplies.

•

Power up VDD_IO, PLL_AVDD, VBAT_RTC (if not applied permanently), VDD_MEM_IO, USB PHY, and SATA PHY

supplies first in any order and then power up VDD_CORE. If required, AVDD_FUSEWR should be powered up afterwards.

•

All the supplies must reach the specified operating conditions before the PORESET can be released.

•

For power down, drop AVDD_FUSEWR to 0 V first, drop VDD_CORE to 0 V, and then drop all other supplies.

•VDD_CORE should not exceed VDD_IO, VDD_MEM_IO, VBAT_RTC, or PLL_AVDDs by more than 0.4 V at any time,

including power-up.

4.2

System and CPU Core AVDD Power Supply Filtering

Each of the independent PLL power supplies require filtering external to the device. The following drawing Figure 58 is a

recommendation for the required filter circuit.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from

nearby circuits.

All traces should be as low impedance as possible, especially ground pins to the ground plane.

The filter for System/Core PLLVDD to VSS should be connected to the power and ground planes, respectively, not fingers of the

planes.

In addition to keeping the filter components for System/Core PLLVDD as close as practical to the body of the MPC5121e as

previously mentioned, special care should be taken to avoid coupling switching power supply noise or digital switching noise

onto the portion of that supply between the filter and the MPC5121e.

Figure 58. Power Supply Filtering

The capacitors for C2 in Figure 58 should be rated X5R or better due to temperature performance. It is recommended to add a

bypass capacitance of at least 1 µF for the VBAT_RTC pin.

4.3

Connection Recommendations

To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to

VDD_IO. Unused active high inputs should be connected to VSS. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD and VSS pins of the MPC5121e/MPC5123.

The unused AVDD_FUSEWR power should be connecetd to VSS directly or via a resistor.

For DDR or LPDDR modes the unused pins MVTT[3:0] for DDR2 Termination voltage can be unconnected.

AVDD device pin

Power supply

source

R1 = 10

C1 = 1

μF

C2 = 0.1

μF

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