MPC5121E datasheet(58/86 Pages) FREESCALE

Numer części	MPC5121E

Szczegółowy opis	e300 Power Architecture processor core

PDF	86 Pages

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Producent	FREESCALE [Freescale Semiconductor, Inc]

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MPC5121E/MPC5123 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 38. Ethernet Timing Diagram – MII Serial Management

Table 34. MII Serial Management Channel Signal Timing

Sym

Description

Min

Max

Unit

SpecID

MDC falling edge to MDIO output delay

A11.10

MDIO (input) to MDC rising edge setup

—

A11.11

MDIO (input) to MDC rising edge hold

—

A11.12

MDC pulse width high1

1 MDC is generated by MPC5121e/MPC5123 with a duty cycle of 50% except when MII_SPEED in the FEC

MII_SPEED control register is changed during operation. See the MPC5121e/MPC5123 Reference Manual.

160

—

A11.13

MDC pulse width low1

160

—

A11.14

MDC period2

2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII

characteristic) by programming the FEC MII_SPEED control register. See the MPC5121e/MPC5123 Reference

Manual.

400

—

A11.15

MDC (Output)

MDIO (Input)

MDIO (Output)

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