MPC5121E datasheet(79/86 Pages) FREESCALE

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System Design Information

MPC5121E/MPC5123 Data Sheet, Rev. 4

Freescale Semiconductor

For a board with a COP (common on-chip processor) connector that accesses the JTAG interface and needs to reset the JTAG

module, only wiring TRST and PORESET is not recommended.

To reset the MPC5121e/MPC5123 via the COP connector, the HRESET pin of the COP should be connected to the HRESET

pin of the MPC5121e/MPC5123. The circuitry shown in Figure 62 allows the COP to assert HRESET or TRST separately,

while any other board sources can drive PORESET.

Table 52. COP/BDM Interface Signals

BDM Pin # MPC5121e/MPC5123 I/O Pin BDM Connector

Internal

Pull Up/Down

External

Pull Up/Down

I/O1

1 With respect to the emulator tool’s perspective:

Input is really an output from the embedded e300 core.

Output is really an input to the core.

—

GND

—

CKSTP_OUT

ckstp_out

—

10 k

Ω Pull-up

—

KEY

—

HRESET

hreset

Pull-up

10 k

Ω Pull-up

—

GND

—

SRESET

sreset

Pull-up

10 k

Ω Pull-up

—

N/C

—

TMS

tms

Pull-up

10 k

Ω Pull-up

CKSTP_IN

ckstp_in

—

10 k

Ω Pull-up

TCK

tck

Pull-up

10 k

Ω Pull-up

6—

VDD2

2 From the board under test, power sense for chip power.

——

—

See Note3

3 HALTED is not available from e300 core.

halted3

——

4TRST

trst

Pull-up

10 k

Ω Pull-up

TDI

tdi

Pull-up

10 k

Ω Pull-up

See Note4

4 Input to the e300 core to enable/disable soft-stop condition during breakpoints. MPC5121e/MPC5123

internally ties CORE_QACK to GND in its normal/functional mode (always asserted).

qack4

——

1TDO

tdo

—

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