UJA1069 datasheet(39/64 Pages) PHILIPS

39 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

39 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

6.13.2 Forced normal mode

For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode

is strictly for evaluation purposes only. In this mode the characteristics as deﬁned in

Section 9 and Section 10 cannot be guaranteed.

In Forced normal mode the SBC behaves as follows:

• SPI access (writing and reading) is blocked

• Watchdog disabled

• Interrupt monitoring disabled

• Reset monitoring disabled

• Reset lengthening disabled

• All transitions to Fail-safe mode are disabled, except a V1 undervoltage for more than

tV1(CLT)

• V1 is started with the long reset time tRSTNL. In case of a V1 undervoltage, a reset is

performed until V1 is restored (normal behavior), and the SBC stays in Forced normal

mode; in case of an overload at V1 > tV1(CLT) Fail-safe mode is entered

• V3 is on; overload protection active

• LIN is in Active mode and cannot switch to Off-line mode

• INH/LIMP pin is HIGH

• SYSINH is HIGH

• EN pin at same level as RSTN pin

Forced normal mode is activated by applying the correct Vth(TEST) input voltage at the

TEST pin during ﬁrst battery connection.

UJA1069 Arkusz danych(PDF) 39 Page - NXP Semiconductors