UJA1069 datasheet(26/64 Pages) PHILIPS

26 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

26 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

Flash mode can be entered only with the watchdog service sequence ‘Normal mode to Flash mode to Normal mode to Flash mode’,

while observing the watchdog trigger rules. With the last command of this sequence the SBC forces a system reset, and enters Start-up

mode to prepare the microcontroller for ﬂash memory download. The four RSS bits in the System Status register reﬂect the reset source

information, conﬁrming the Flash entry sequence. By using the Initializing Flash mode (within tWD(init) after system reset) the SBC will

now successfully enter Flash mode.

[2]

See Section 6.13.1.

Table 4.

Mode register bit description (bits 15 to 12 and 5 to 0)

Bit

Symbol

Description

Value

Function

15 and 14

A1, A0

select Mode register

RRS

Read Register

Select

read System Diagnosis register

read System Status register

Read Only

read selected register without writing to Mode register

read selected register and write to Mode register

11 to 6

NWP[5:0]

see Table 5

5 to 3

OM[2:0]

Operating Mode

001

Normal mode

010

Standby mode

011

initialize Flash mode[1]

100

Sleep mode

101

initialize Normal mode

110

leave Flash mode

111

Flash mode [1]

SDM

Software

Development

Mode

Software development mode enabled[2]

normal watchdog, interrupt, reset monitoring and fail-safe

behavior

Enable

EN output pin HIGH

EN output pin LOW

reserved

reserved for future use; should remain cleared to ensure

compatibility with future functions which might use this bit

UJA1069 Arkusz danych(PDF) 26 Page - NXP Semiconductors

UJA1069 Arkusz danych(HTML) 26 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

Arkusz danych Pobierz

Link URL