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UJA1069 Arkusz danych(PDF) 32 Page - NXP Semiconductors |
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UJA1069 Arkusz danych(HTML) 32 Page - NXP Semiconductors |
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32 / 64 page  UJA1069_2 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 02 — 5 March 2007 32 of 64 NXP Semiconductors UJA1069 LIN fail-safe system basis chip 6.12.8 System Configuration register and System Configuration Feedback register These registers allow configuration of the behavior of the SBC, and allow the settings to be read back. Table 9. Interrupt register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 01 read Interrupt register 13 RRS Read Register Select 1 12 RO Read Only 1 read the Interrupt register without writing to the Interrupt Enable register 0 read the Interrupt register and write to the Interrupt Enable register 11 WTI Watchdog Time-out Interrupt 1 a watchdog overflow during Standby mode has caused an interrupt (interrupt-based cyclic wake-up feature) 0 no interrupt 10 OTI OverTemperature Interrupt 1 the temperature warning status (TWS) has changed 0 no interrupt 9 - reserved 0 reserved for SBCs with CAN transceiver 8 SPIFI SPI clock count Failure Interrupt 1 wrong number of CLK cycles (more than, or less than 16) during SPI access 0 no interrupt; SPI access is ignored if the number of CLK cycles does not equal 16 7 BATFI BAT Failure Interrupt 1 falling edge at pin SENSE has forced an interrupt 0 no interrupt 6 VFI Voltage Failure Interrupt 1 V1D or V3D has been cleared 0 no interrupt 5 - reserved 0 reserved for SBCs with CAN transceiver 4 LINFI LIN Failure Interrupt 1 LIN failure status has changed 0 no interrupt 3 WI Wake-up Interrupt 1 a negative edge at pin WAKE has been detected 0 no interrupt 2 WDRI Watchdog Restart Interrupt 1 A watchdog restart during watchdog OFF has caused an interrupt 0 no interrupt 1 - reserved 0 reserved for SBCs with CAN transceiver 0 LINI LIN Wake-up Interrupt 1 LIN wake-up event has caused an interrupt 0 no interrupt Table 10. System Configuration and System Configuration Feedback register bit description Bit Symbol Description Value Function 15 and 14 A1, A0 register address 10 select System Configuration register 13 RRS Read Register Select 1 read the General Purpose Feedback register 0 0 read the System Configuration Feedback register |
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