UJA1069 datasheet(44/64 Pages) PHILIPS

44 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

44 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

IV1

output current

capability

VBAT14 = 9 V to 27 V;

δV

V1 = 0.05 × VV1(nom)

−200

−135

−120

VBAT14 = 9 V to 27 V;

V1 shorted to GND

−200

−110

VBAT14 =6V to8V;

δV

V1 = 0.05 × VV1(nom)

−250

VBAT14 = 5.5 V;

δV

V1 = 0.05 × VV1(nom)

−150

VBAT14 = 5.5 V;

δV

V1 = 0.25 × VV1(nom)

−250

Zds(on)

regulator impedance

between pins BAT14

and V1

VBAT14 = 4 V to 5 V

Ω

Voltage source; pin V3

VBAT42-V3(drop)

VBAT42 to VV3 voltage

drop

VBAT42 = 9 V to 52 V;

IV3 = −20 mA

1.0

Idet(OL)(V3)

overload current

detection threshold

VBAT42 = 9 V to 52 V

−165

−60

IL

leakage current

VV3 = 0 V; V3C[1:0] = 00

µA

System inhibit output; pin SYSINH

VBAT42-SYSINH(drop) VBAT42 to VSYSINH

voltage drop

ISYSINH = −0.2 mA

1.0

2.0

IL

leakage current

VSYSINH =0V

µA

Inhibit/limp-home output; pin INH/LIMP

VBAT14-INH(drop)

VBAT14 to VINH

voltage drop

IINH/LIMP = −10 µA;

ILEN = ILC = 1

0.7

1.0

IINH/LIMP = −200 µA;

ILEN = ILC = 1

1.2

2.0

Io(INH/LIMP)

output current

capability

VINH/LIMP = 0.4 V;

ILEN = 1; ILC = 0

0.8

IL

leakage current

VINH/LIMP = 0 V to VBAT14;

ILEN = 0

--5

µA

Wake input; pin WAKE

Vth(WAKE)

wake-up voltage

threshold

2.0

3.3

5.2

IWAKE(pu)

pull-up input current

VWAKE =0V

−25

−1.3

µA

Serial peripheral interface inputs; pins SDI, SCK and SCS

VIH(th)

HIGH-level input

threshold voltage

0.7

× VV1

-VV1 + 0.3

VIL(th)

LOW-level input

threshold voltage

−0.3

+0.3

× V

Rpd(SCK)

pull-down resistor at

pin SCK

VSCK =2V; VV1 ≥ 2 V

130

400

Ω

Table 25.

Static characteristics …continued

Tvj = −40 °C to +150 °C, VBAT42 = 5.5 Vto52 V;VBAT14 = 5.5 Vto27 V;VBAT42 ≥ VBAT14 − 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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