UJA1069 datasheet(46/64 Pages) PHILIPS

46 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

46 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

LIN-bus line; pin LIN

Vo(dom)

LIN dominant output

voltage

Active mode;

VBAT42 =7Vto18V;

LDC = 0; t < tTXDL(dom)(dis);

VTXDL =0V;

RBAT42-LIN = 500 Ω

0.20

VBAT42

Active mode;

VBAT42 =7.6 Vto18V;

LDC = 1; t < tTXDL(dom)(dis);

VTXDL =0V; ILIN =40mA

0.7

1.4

2.1

ILIH

HIGH-level input

leakage current

VLIN =VBAT42; VTXDL =VV1

−10

+10

µA

VBAT42 =8V;

VLIN =8Vto18V;

VTXDL =VV1

−10

+10

µA

ILIL

LOW-level input

leakage current

VBAT42 = 12 V; VLIN =0V;

VTXDL =VV1

−100

µA

Io(sc)

short-circuit output

current

Active mode;

VLIN =VBAT42 =12V;

VTXDL =0V; t<tTXDL(dom)(dis);

LDC=0

Active mode;

VLIN =VBAT42 =18V;

VTXDL =0V; t<tTXDL(dom)(dis);

LDC=0

Vth(dom)

receiver dominant

state

VBAT42 = 7 V to 27 V

0.4

VBAT42

Vth(reces)

receiver recessive

state

VBAT42 = 7 V to 27 V

0.6

VBAT42

--V

Vth(hyst)

receiver threshold

voltage hysteresis

VBAT42 = 7 V to 27 V

0.05

VBAT42

0.175

VBAT42

Vth(cen)

receiver threshold

voltage center

VBAT42 = 7 V to 27 V

0.475

VBAT42

0.500

VBAT42

0.525

VBAT42

input capacitance

[3] --10

leakage current

VLIN =0Vto18V

VBAT42 =0V

−50

µA

VGND =VBAT42 =12V

−10

+10

µA

LIN-bus termination resistor connection; pin RTLIN

VRTLIN

RTLIN output

voltage

Active mode; IRTLIN = −10 µA;

VBAT42 = 7 V to 27 V

VBAT42 −

1.0

VBAT42 −

0.7

VBAT42 −

0.2

Off-line mode;

IRTLIN = −10 µA;

VBAT42 =7Vto27V

VBAT42 −

1.2

VBAT42 −

1.0

-V

∆V

RTLIN

RTLIN load

regulation

Active mode;

IRTLIN = −10 µAto −10 mA;

VBAT42 = 7 V to 27 V

0.65

Table 25.

Static characteristics …continued

Tvj = −40 °C to +150 °C, VBAT42 = 5.5 Vto52 V;VBAT14 = 5.5 Vto27 V;VBAT42 ≥ VBAT14 − 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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