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UJA1069 Arkusz danych(PDF) 27 Page - NXP Semiconductors

Numer części UJA1069
Szczegółowy opis  LIN fail-safe system basis chip
PDF  64 Pages
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UJA1069 Arkusz danych(HTML) 27 Page - NXP Semiconductors

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UJA1069_2
© NXP B.V. 2007. All rights reserved.
Preliminary data sheet
Rev. 02 — 5 March 2007
27 of 64
NXP Semiconductors
UJA1069
LIN fail-safe system basis chip
Table 5.
Mode register bit description (bits 11 to 6)[1]
Bit
Symbol
Description
Value
Time
Normal
mode (ms)
Standby
mode (ms)
Flash mode
(ms)
Sleep mode
(ms)
11 to 6
NWP[5:0]
Nominal
Watchdog Period
WDPRE = 00 (as
set in the Special
Mode register)
00 1001
4
20
20
160
00 1100
8
40
40
320
01 0010
16
80
80
640
01 0100
32
160
160
1024
01 1011
40
320
320
2048
10 0100
48
640
640
3072
10 1101
56
1024
1024
4096
11 0011
64
2048
2048
6144
11 0101
72
4096
4096
8192
11 0110
80
OFF[2]
8192
OFF[3]
Nominal
Watchdog Period
WDPRE = 01 (as
set in the Special
Mode register)
00 1001
6
30
30
240
00 1100
12
60
60
480
01 0010
24
120
120
960
01 0100
48
240
240
1536
01 1011
60
480
480
3072
10 0100
72
960
960
4608
10 1101
84
1536
1536
6144
11 0011
96
3072
3072
9216
11 0101
108
6144
6144
12288
11 0110
120
OFF[2]
12288
OFF[3]
Nominal
Watchdog Period
WDPRE = 10 (as
set in the Special
Mode register)
00 1001
10
50
50
400
00 1100
20
100
100
800
01 0010
40
200
200
1600
01 0100
80
400
400
2560
01 1011
100
800
800
5120
10 0100
120
1600
1600
7680
10 1101
140
1560
1560
10240
11 0011
160
5120
5120
15360
11 0101
180
10240
10240
20480
11 0110
200
OFF[2]
20480
OFF[3]



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