UJA1069 datasheet(28/64 Pages) PHILIPS

28 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

28 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for fosc = 512 kHz.

[2]

See Section 6.4.4.

[3]

The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is

immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry

without dips on V1. See Section 6.4.4.

6.12.4 System Status register

This register allows status information to be read back from the SBC. This register can be

read in all modes.

11 to 6

NWP[5:0]

Nominal

Watchdog Period

WDPRE = 11 (as

set in the Special

Mode register)

00 1001

560

00 1100

140

1120

01 0010

280

2240

01 0100

112

560

3584

01 1011

140

1120

7168

10 0100

168

2240

10752

10 1101

196

3584

14336

11 0011

244

7168

21504

11 0101

252

14336

28672

11 0110

280

OFF[2]

28672

OFF[3]

Table 5.

Mode register bit description (bits 11 to 6)[1] …continued

Bit

Symbol

Description

Value

Time

Normal

mode (ms)

Standby

mode (ms)

Flash mode

(ms)

Sleep mode

(ms)

Table 6.

System Status register bit description

Bit

Symbol

Description

Value

Function

15 and 14

A1, A0

read System Status register

RRS

Read Register Select

Read Only

read System Status register without writing to Mode

read System Status register and write to Mode register

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