UJA1069 datasheet(31/64 Pages) PHILIPS

31 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

31 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

[1]

This bit is cleared automatically upon each overﬂow event. It has to be set in software each time the interrupt behavior is required

(fail-safe behavior).

[2]

WEN (in the System Conﬁguration register) has to be set to activate the WAKE port function globally.

6.12.7 Interrupt register

The Interrupt register allows the cause of an interrupt event to be read. The register is

cleared upon a read access and upon any reset event. Hardware ensures that no interrupt

event is lost in case there is a new interrupt forced while reading the register. After reading

the Interrupt register pin INTN is released for tINTN to guarantee an edge event at pin

INTN.

The interrupts can be classiﬁed into two groups:

• Timing critical interrupts which require immediate reaction (SPI clock count failure

which needs a new SPI command to be resent immediately, and a BAT failure which

needs critical data to be saved immediately into the nonvolatile memory)

• Interrupts which do not require an immediate reaction (overtemperature and LIN

failures, V1 and V3 failures and the wake-ups via LIN and WAKE. These interrupts will

be signalled in Normal mode to the microcontroller once per watchdog period

(maximum); this prevents overloading the microcontroller with unexpected interrupt

events (e.g. a chattering LIN failure). However, these interrupts are reﬂected in the

interrupt register

BATFIE

BAT Failure Interrupt

Enable

falling edge at SENSE forces an interrupt

no interrupt forced

VFIE

Voltage Failure Interrupt

Enable

clearing of V1D or V3D forces an interrupt

no interrupt forced

reserved

reserved for SBCs with CAN transceiver

LINFIE

LIN Failure Interrupt

Enable

any change of the LIN Failure status bits forces an interrupt

no interrupt forced

WIE

WAKE Interrupt

Enable[2]

a negative edge at pin WAKE generates an interrupt in

Normal mode, Flash mode or Standby mode

a negative edge at pin WAKE generates a reset in Standby

mode; no interrupt in any other mode

WDRIE

Watchdog Restart

Interrupt Enable

a watchdog restart during watchdog OFF generates an

interrupt

no interrupt forced

reserved

reserved for SBCs with CAN transceiver

LINIE

LIN Interrupt Enable

LIN-bus event results in a wake-up interrupt in Standby

mode and in Normal or Flash mode (unless LIN is in Active

mode already)

LIN-bus event results in a reset in Standby mode; no

interrupt in any other mode

Table 8.

Interrupt Enable and Interrupt Enable Feedback register bit description …continued

Bit

Symbol

Description

Value

Function

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