ATmega325P datasheet(101/364 Pages) ATMEL

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101

8023F–AVR–07/09

ATmega325P/3250P

The edge detector generates one clk

T1/clkT0 pulse for each positive (CSn2:0 = 7) or negative

(CSn2:0 = 6) edge it detects.

Figure 14-8. T1/T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T1/T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least

one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 14-9. Prescaler for Timer/Counter0 and Timer/Counter1

(1)

Note:

1. The synchronization logic on the input pins (

T1/T0) is shown in Figure 14-8.

Tn_sync

(To Clock

Select Logic)

Edge Detector

Synchronization

clk

I/O

PSR10

Clear

clk

I/O

Synchronization

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