ATmega325P datasheet(105/364 Pages) ATMEL

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105

8023F–AVR–07/09

ATmega325P/3250P

• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the ”TIFR0 –

Timer/Counter 0 Interrupt Flag Register” on page 105.

• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the ”TIFR0 – Timer/Counter

0 Interrupt Flag Register” on page 105.

14.10.5

TIFR0 – Timer/Counter 0 Interrupt Flag Register

• Bit 1 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the

data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic

one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt

Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed.

• Bit 0 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared

by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-

rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In

phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at

0x00.

14.10.6

GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR2 and PSR10 bits is kept, hence keeping the corresponding pres-

caler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and

can be configured to the same value without the risk of one of them advancing during configura-

tion. When the TSM bit is written to zero, the PSR2 and PSR10 bits are cleared by hardware,

and the Timer/Counters start counting simultaneously.

Bit

765

4321

0x15 (0x35)

–

–OCF0A

TOV0

TIFR0

Read/Write

RRRR

R/W

Initial Value

000

0000

Bit

0x23 (0x43)

TSM

–

PSR2

PSR10

GTCCR

Read/Write

R/W

Initial Value

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