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CY8C53 Arkusz danych(PDF) 45 Page - Cypress Semiconductor |
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CY8C53 Arkusz danych(HTML) 45 Page - Cypress Semiconductor |
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45 / 106 page ![]() PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 45 of 106 8. Analog Subsystem The analog programmable system creates application specific combinations of both standard and advanced analog signal processing blocks. These blocks are then interconnected to each other and also to any pin on the device, providing a high level of design flexibility and IP security. The features of the analog subsystem are outlined here to provide an overview of capabilities and architecture. Flexible, configurable analog routing architecture provided by analog globals, analog mux bus, and analog local buses Successive approximation (SAR) ADC Two 8-bit DACs that provide either voltage or current output Four comparators with optional connection to configurable LUT outputs Two configurable switched capacitor/continuos time (SC/CT) blocks for functions that include opamp, unity gain buffer, programmable gain amplifier, transimpedance amplifier, and mixer Two opamps for internal use and connection to GPIO that can be used as high current output buffers CapSense subsystem to enable capacitive touch sensing Precision reference for generating an accurate analog voltage for internal analog blocks Figure 8-1. Analog Subsystem Block Diagram The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and various analog resources and also connections from one analog resource to another. PSoC Creator also provides component libraries that allow you to configure the various analog blocks to perform application specific functions (PGA, transimpedance amplifier, voltage DAC, current DAC, and so on). The tool also generates API interface libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory. A nalog In te rfa c e CM P CM P CM P CM P C a p S en se S u b syste m DS I A rra y Clo c k D istribu tion De cim a to r C onfig & S tatus R egisters PH U B CP U C o m parators GP IO Po rt GP IO Po rt DA C DA C A N A L O G R O U T I N G A N A L O G R O U T I N G SC /C T Blo c k SC/C T Blo c k SAR AD C P recision R e fe rence [+] Feedback |
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