CY8C53_11 datasheet(11/106 Pages) CYPRESS

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PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 11 of 106

Bit-band support. Atomic bit-level write and read operations.

Unaligned data storage and access. Contiguous storage of

data of different byte lengths.

Operation at two privilege levels (privileged and user) and in

two modes (thread and handler). Some instructions can only

be executed at the privileged level. There are also two stack

pointers: Main (MSP) and Process (PSP). These features

support a multitasking operating system running one or more

user-level processes.

Extensive interrupt and system exception support.

4.1.2 Cortex-M3 Operating Modes

The Cortex-M3 operates at either the privileged level or the user

level, and in either the thread mode or the handler mode.

Because the handler mode is only enabled at the privileged level,

there are actually only three states, as shown in Table 4-1.

At the user level, access to certain instructions, special registers,

configuration registers, and debugging components is blocked.

Attempts to access them cause a fault exception. At the

privileged level, access to all instructions and registers is

allowed.

The processor runs in the handler mode (always at the privileged

level) when handling an exception, and in the thread mode when

not.

4.1.3 CPU Registers

The Cortex-M3 CPU registers are listed in Table 4-2. Registers

R0-R15 are all 32 bits wide.

Table 4-1. Operational Level

Condition

Privileged

User

Running an exception

Handler mode

Not used

Running main program Thread mode

Thread mode

Table 4-2. Cortex M3 CPU Registers

Description

R0-R12

General purpose registers R0-R12 have no

special architecturally defined uses. Most

instructions that specify a general purpose

Low Registers: Registers R0-R7 are acces-

sible by all instructions that specify a general

purpose register.

High Registers: Registers R8-R12 are acces-

sible by all 32-bit instructions that specify a

general purpose register; they are not acces-

sible by all 16-bit instructions.

R13

R13 is the stack pointer register. It is a banked

pointers: the Main Stack Pointer (MSP) and the

Process Stack Pointer (PSP). The PSP is used

only when the CPU operates at the user level in

thread mode. The MSP is used in all other

privilege levels and modes. Bits[0:1] of the SP

are ignored and considered to be 0, so the SP is

always aligned to a word (4 byte) boundary.

R14

R14 is the Link Register (LR). The LR stores the

return address when a subroutine is called.

R15

R15 is the Program Counter (PC). Bit 0 of the PC

is ignored and considered to be 0, so instructions

are always aligned to a half word (2 byte)

boundary.

xPSR

The Program status registers are divided into

three status registers, which are accessed either

together or separately:

Application Program Status Register (APSR)

holds program execution status bits such as

zero, carry, negative, in bits[27:31].

Interrupt Program Status Register (IPSR)

holds the current exception number in bits[0:8].

Execution Program Status Register (EPSR)

holds control bits for interrupt continuable and

IF-THEN instructions in bits[10:15] and

[25:26]. Bit 24 is always set to 1 to indicate

Thumb mode. Trying to clear it causes a fault

exception.

PRIMASK

A 1-bit interrupt mask register. When set, it

allows only the nonmaskable interrupt (NMI) and

hard fault exception. All other exceptions and

interrupts are masked.

FAULTMASK A 1-bit interrupt mask register. When set, it

allows only the NMI. All other exceptions and

interrupts are masked.

BASEPRI

A register of up to nine bits that define the

masking priority level. When set, it disables all

interrupts of the same or higher priority value. If

set to 0 then the masking function is disabled.

CONTROL

A 2-bit register for controlling the operating

mode.

Bit 0: 0 = privileged level in thread mode,

1 = user level in thread mode.

Bit 1: 0 = default stack (MSP) is used,

1 = alternate stack is used. If in thread mode or

user level then the alternate stack is the PSP.

There is no alternate stack for handler mode; the

bit must be 0 while in handler mode.

Table 4-2. Cortex M3 CPU Registers (continued)

Description

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