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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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CY8C53 Arkusz danych(PDF) 23 Page - Cypress Semiconductor |
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CY8C53 Arkusz danych(HTML) 23 Page - Cypress Semiconductor |
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23 / 106 page  PRELIMINARY PSoC® 5: CY8C53 Family Datasheet Document Number: 001-66237 Rev. *A Page 23 of 106 6.2.1 Power Modes PSoC 5 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. PSoC 5 power modes, in order of decreasing power consumption are: Active Alternate Active Sleep Hibernate Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and Real Time Clock functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes. Sleep and hibernate modes should not be entered until all VDDIO supplies are at valid voltage levels. Note 6. Bus clock off. Execute from CPU instruction buffer at 6 MHz. See Table 11-2 on page 59. Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all peripherals available (programmable) Wakeup, reset, manual register entry Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Alternate Active Similar to Active mode, and is typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off Manual register entry Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Sleep All subsystems automatically disabled Manual register entry PICU, RTC, CTW, LVD ILO/kHzECO Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Hibernate All subsystems automatically disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Manual register entry PICU Only hibernate regulator active. Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Wakeup Time Current (Typ) Code Execution Digital Resources Analog Resources Clock Sourc- es Available Wakeup Sources Reset Sources Active – 5 mA[6] Yes All All All – All Alternate Active – – User defined All All All – All Sleep 20 µs typ 3 µA No None None ILO/kHzECO PICU, RTC, CTW, LVD XRES, LVD, WDR Hibernate <100 µs 1 µA No None None None PICU XRES [+] Feedback |
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