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PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 55 of 106

9.1 Debug Port Acquisition

Prior to programming or debugging, the debug port must be

acquired. There is a time window after reset within which the Port

Acquire must be completed. This window is initially 8 µs; if eight

clocks are detected on the SWDCK line within the 8 µs period,

the time window will then be extended to 400 µs to complete the

port acquire operation. The port acquire key must be transmitted

over one of the two SWD pin pairs; see SWD Interface. For a

detailed description of the acquire key sequence, refer to the

Technical Reference Manual

9.2 SWD Interface

SWD uses two pins, either two port 1 pins or the USBIO D+ and

D- pins. The USBIO pins are useful for in system programming

of USB solutions that would otherwise require a separate

programming connector. One pin is used for the data clock and

the other is used for data input and output. SWD can be enabled

on only one of the pin pairs at a time. SWD is used for debugging

or for programming the flash memory. In addition, the SWD

interface supports the SWV trace output. The SWD interface

also includes the SWV interface, see SWV Interface on page 56.

When using the SWD/SWV pins as standard GPIO, make sure

that the GPIO functionality and PCB circuits do not interfere with

SWD/SWV use. The SWV trace output is automatically activated

whenever the SWD is activated.

Figure 9-1. SWD Interface Connections between PSoC 5 and Programmer

VSSD, VSSA

VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3

1, 2, 3

SWDCK (P1[1] or P15[7])

SWDIO (P1[0] or P15[6])

XRES

GND

SWDCK

SWDIO

XRES

Host Programmer

PSoC 5

VDD

1 The voltage levels of the Host Programmer and the PSoC5 voltage domains involved in programming should be

the same. XRES pin is powered by

VDDIO1. The USB SWD pins are powered by VDDD. So for

programming using the USB SWD pins with XRES pin, the

VDDD, VDDIO1 of PSoC 5 should be at the same voltage

level as Host

VDD. Rest of PSoC 5 voltage domains (VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage

level as host Programmer. The Port 1 SWD pins are powered by

VDDIO1. So VDDIO1 of PSoC 5 should be at same

voltage level as host

VDD for Port 1 SWD programming. Rest of PSoC 5 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2,

VDDIO3) need not be at the same voltage level as host Programmer.

2 Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 5.

3 For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have

the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 5. This may typically require

external interface circuitry to toggle power which will depend on the programming setup. The power

supplies can be brought up in any sequence, however, once stable, VDDA must be greater than or

equal to all other supplies.

4 When USB SWD pins are used for Programming, the P1[1] SWDCK pin must be externally connected to Ground

using external pull-down resistor (around 100 K resistor). This is required for P15[7] SWDCK signal to be seen by

PSoC 5's internal logic.

VDD

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