CY8C53_11 datasheet(28/106 Pages) CYPRESS

28 / 106 page

PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 28 of 106

Figure 6-9. SIO Input/Output Block Diagram

Figure 6-10. USBIO Block Diagram

Drive

Logic

PRT[x]DM0

PRT[x]DR

Digital Output Path

Digital Input Path

PRT[x]SLW

PRT[x]DM1

PRT[x]DM2

Digital System Output

PRT[x]BYP

PRT[x]BIE

Bidirectional Control

Pin Interrupt Signal

Digital System Input

PRT[x]PS

Input Buffer Disable

Interrupt

Logic

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Slew

Cntl

PRT[x]SYNC_OUT

PRT[x]DBL_SYNC_IN

PICU[x]INTSTAT

PRT[x]SIO_DIFF

Buffer

Thresholds

Driver

Vhigh

PRT[x]SIO_CFG

PRT[x]SIO_HYST_EN

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

Reference Level

Drive

Logic

USBIO_CR1[4,5]

Digital Output Path

Digital Input Path

Digital System Output

PRT[x]BYP

Pin Interrupt Signal

Digital System Input

USBIO_CR1[0,1]

Interrupt

Logic

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

PRT[x]DBL_SYNC_IN

PICU[x]INTSTAT

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

Vddd

5 k

1.5 k

D+ pin only

USBIO_CR1[2]

USBIO_CR1[3]

USBIO_CR1[6]

USBIO_CR1[7]

USB or I/O

D+ 1.5 k

D+D- 5 k

Open Drain

PRT[x]SYNC_OUT

USB SIE Control for USB Mode

USB Receiver Circuitry

Vddd

[+] Feedback

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