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QG80331M667 Arkusz danych(PDF) 11 Page - Intel Corporation |
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QG80331M667 Arkusz danych(HTML) 11 Page - Intel Corporation |
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11 / 67 page  Specification Update 11 Intel® 80331 I/O Processor Summary Table of Changes 25 XXX XX X 25 No Fix Boundary scan multi-chip module implementation 26 XXX XX X 25 No Fix Auto refresh command also generates a Precharge All command on DDR bus 27 X 26 Fixed SERR# set to incorrect voltage 28 X 26 Fixed M66EN set to incorrect voltage 29 X 26 Fixed P_INT[D:A]# not operating correctly 30 X 26 Fixed Secondary bus may not initialize correctly at 100 MHz PCI-X or 133 MHz PCI-X 31 XXX XX X 26 No Fix Coalesced writes to 32-bit memory can cause data corruption 32 XXX XX X 27 No Fix ATU passing rules operation in PCI mode 33 XX 27 Fixed S_INT[D:A]# pull-ups disabled by Internal Bus Reset 34 XX 27 Fixed MCU Preemption Control does not properly manage the byte count 35 XX 28 Fixed I2C unit hang condition 36 XXX XX X 28 No Fix VPD Data Register bit 19 is not read/write 37 XX 29 Fixed Intel XScale® Core lockup condition 38 XX 30 Fixed 32-bit region write corrupts ECC immediately after 64-bit Read-Modify-Write 39 X 30 Fixed Reset straps incorrectly sampled on the secondary reset 40 XX 31 Fixed PCI-X to PCI Memory Read double-word near 1MB boundary may cause the system to hang 41 XX 31 Fixed PCI-X to PCI Memory Read Block across 1MB boundary may cause data corruption 42 XXX XX X 32 No Fix DMA CRC result is byte reversed 43 XXX XX X 32 No Fix CRC corruption on PCI-to-local DMA transfers 44 XXX X 32 Fixed Byte Count Modified bit set to 1 45 XXX X 33 Fixed Corrupted byte count and data when crossing 1 MByte boundary in PCI-X to PCI mode 46 XXX X 33 Fixed PCI-X to PCI Memory Read with 4 K byte count and unaligned starting address 47 XXX 34 Fixed VCCDDR (VCC25/VCC18) Current Spike 48 XXX X 35 Fixed Bridge PCI ordering rule violation 49 XXX XX X 35 No Fix ATU claims PCI commands 8 and 9 when issued as Dual Address Cycle (DAC) 50 XXX XX X 36 No Fix Secondary bus PCI RST# pulse prior to the rising edge of P_RST# 51 XX 36 Fixed Slow edge rates observed when 80331 is driving the primary bus 52 XXX X 37 Fixed Enabling the core-to-memory port can cause a stall condition Non-Core Errata (Sheet 2 of 3) No. Steppings Page Status Errata A-1 B-0 C-0 C-1 D-0 D-1 |
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