QG80331M667 datasheet(19/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

CAS latency of three not supported for DDR-II On-Die Termination (ODT)

Problem:

For DDR-II memory with a CAS Latency (CL) of three, the memory controller unit (MCU) does

not provide the proper timing for the On-Die Termination signals (ODT[1:0]). The JEDEC DDR-II

SDRAM Specification, September 2002, states that ODT must be driven one cycle prior to the write

command, but the MCU does not meet this timing.

Implication:

CAS latency of 3 is not supported in the 80331, therefore minimal performance impact as

compared to CAS latency of 4.

Workaround:

Use CAS latency = 4 or do not use ODT feature.

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

Upper PCI signals on Secondary PCI bus are not driven low during reset

Problem:

PCI requires the central resource to provide valid logic states on AD[63:32], C/BE[7:4]# and PAR64

during reset, and that they may only be driven to zero. The S_AD[63:32], S_C/BE[7:4]#, S_PAR64

on the secondary PCI bus are not driven to zero during secondary bridge PCI-X initialization; instead,

these pins are tri-stated, “Z”. This is not a violation of the PCI Local Bus Specification, Revision 2.3.

Implication:

Some PCI targets may not operate correctly, when they require these signals to be zero during reset.

Workaround:

No workaround.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

Memory Controller Unit does not properly support 32-bit memory

configurations

Problem:

The memory controller unit (MCU) incorrectly stores the row address used in the page miss/page

hit look up table. The result of this can cause the MCU to incorrectly determine a page hit or miss.

When this occurs, it causes aliasing to an incorrect row of DDR SDRAM.

Implication:

32-bit memory cannot be used with A-1 stepping.

Workaround:

No workaround. Use a 64-bit memory subsystem.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

Legacy Power Fail Mechanism does not work

Problem:

For previous I/O processor generations, an external clock was required to maintain the incoming

PCI clock (P_CLK) long enough for the power fail sequence to be sent to the memory. This is what

is referred to as ‘legacy power fail’. The internal control circuit that enables the legacy power fail

method is broken.

Implication:

Legacy power fail cannot be used.

Workaround:

For 80331, a new feature was added which keeps internal clocks running on power fail.

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

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