QG80331M667 datasheet(44/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Core Errata

Performance Monitor Unit event 0x1 can be incremented erroneously by

unrelated events

Event 0x1 in the performance monitor unit (PMU) can be used to count cycles in which the

instruction cache cannot deliver an instruction. The only cycles counted should be those due to an

instruction cache miss or an instruction TLB miss. The following unrelated events in the core, also

causes the corresponding count to increment when event number 0x1 is being monitored:

• Any architectural event (e.g., IRQ, data abort)

• MSR instructions which alter the CPSR control bits.

• Some branch instructions, including indirect branches and those mispredicted by the BTB.

• CP15 MCR instructions to registers 7, 8, 9, or 10 which involve the instruction cache or the

instruction TLB.

Each of the preceding items may cause the performance monitoring count to increment several

times. The resulting performance monitoring count may be higher than expected, when the

preceding items occur, but should never be lower than expected.

Workaround:

There is no way to obtain the correct number of cycles stalled due to instruction cache misses and

instruction TLB misses. Extra counts, due to branch instructions mispredicted by the BTB, may be

one component of the unwanted count that can be filtered out.

The number of mispredicted branches also can be monitored using performance monitoring event

0x6 during the same time period as event 0x1. The mispredicted branch number then can be

subtracted from the instruction cache stall number generated by the performance monitor to get a

value closer to the correct one. This workaround only addresses counts contributed by branches

that the BTB is able to predict.

All the items in the preceding bulleted list still affect the count. Depending on the nature of the

code being monitored, this workaround may have limited value.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

In Special Debug State, back-to-back memory operations — where the first

instruction aborts — may cause a hang

Problem:

When back-to-back memory operations occur in the Special Debug State (SDS, used by ICE and

Debug vendors) and the first memory operation gets a precise data abort, the first memory

operation is correctly cancelled and no abort occurs. Depending on the timing, however, the second

memory operation may not work correctly. The data cache may internally cancel the second

operation, but the register file may have scoreboarded registers for that second memory operation.

The effect is that the core may hang (due to a permanently scoreboarded register) or that a store

operation may be incorrectly cancelled.

Workaround:

In Special Debug State, any memory operation that may cause a precise data abort should be

followed by a write-buffer drain operation. This precludes further memory operations from being

in the pipe when the abort occurs. Load Multiple/Store Multiple that may cause precise data aborts

should not be used.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

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