QG80331M667 datasheet(21/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

10.

PCI-66 Mode violates PCI AC Timings

Problem:

The PCI Local Bus Specification, Revision 2.3 states a setup time of 3 ns for PCI-66 mode. The

80331 A-1 step has estimated the setup time to be in the range of 3.5 ns to 4 ns, which violates the

PCI Local Bus Specification, Revision 2.3.

Implication:

Some PCI 66 MHz targets may not function correctly with A-1 stepping.

Workaround:

Use PCI-33 or PCI-X modes for initial development on A-1 stepping.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

11.

Reserved bits in the Modem Status Register incorrectly generate interrupts

Problem:

Bits[3:1] in the UART Modem Status Register are reserved bits. These reserved bits are incorrectly

tied to the asserted state therefore generate false interrupts when the Modem Interrupt Enable bit

(UxIER.3) is set. However, the reserved bits only generate the false interrupt once. This happens

the cycle after the UART unit is enabled (UxIER.6) and the Modem Status Interrupts are enabled

(UxIER.3). Once the Modem Interrupt Register is read no more false interrupts occur.

Implication:

A false interrupt can occur.

Workaround:

Software needs to read the Modem Status Register to determine proper interrupt sources.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

12.

P_REQ# not de-asserted during idle

Problem:

The P_REQ# signal stays asserted during bus idle instead of de-asserting as required by PCI Local

Bus Specification, Revision 2.3. For example, when a PCI target asserts STOP#, the P_REQ#

signal de-asserts one clock later than it should. The P_REQ# should have been de-asserted during

the idle cycle.

Implication:

May cause conflict with other PCI agents.

Workaround:

Use a system arbiter that does not care when this condition occurs.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

13.

Chassis/Slot PCI Extended Capability is not valid

Problem:

The Chassis/Slot PCI extended capability cannot be configured, and therefore the capability is not

valid and needs to be removed from the capability chain. The Chassis/Slot capability registers at

D4h - D7h needs to be listed as reserved.

Implication:

Invalid capability information provided to the host.

Workaround:

Do not use Chassis/Slot PCI Extended Capability.

Status:

Fixed. Fixed in B-0 stepping. The fix is to change the capability pointer at 34h to point to the next

capability pointer (Power Management) at DCh, instead of D4h. D4h is to return zero when read.

See the Table , “Summary Table of Changes” on page 9.

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