QG80331M667 datasheet(26/67 Pages) INTEL

26 / 67 page

Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

27.

SERR# set to incorrect voltage

Problem:

SERR# is being driven to 1 V. The 80331 might detect SERR# being asserted during boot-up and

does not detect SERR# assertion when a device on the PCI-X bus asserts SERR#.

Implication:

The 80331 falsely detects and logs SERR# assertion during boot-up, due to the SERR# pin being

held at 1 V, which the 80331 detects as a logic low (asserted). Devices assert SERR# for a

minimum of one clock when an SERR# occurs. Since SERR# is being held low, devices asserting

SERR# are not detected by the 80331.

Workaround:

Putting a 34–39

Ω pull-up resistor on SERR# might work; however, some add-in cards do not have

the drive strength to pull-down against this pull-up, and therefore cannot reliably generate SERR#

in the system. An alternative workaround is to have software mask SERR# assertion in the ATU or

bridge.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

28.

M66EN set to incorrect voltage

Problem:

The M66EN signals do not get set to the appropriate level with or without an add-in card present.

M66EN should be at 3.3 V without an add-in card present.

Implication:

Prevents auto-detection of 66 MHz PCI devices. Forces the bus speed to 33 MHz when not in

PCI-X mode and only impacts busses that should be set to 66 MHz PCI.

Workaround:

Use a 34-39 ohm pull-up resistor on the M66EN signals.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

29.

P_INT[D:A]# not operating correctly

Problem:

The P_INT[D:A]# signals only rise to ~1 V at power-on.

Implication:

P_INT[D:A]# interrupt signals can cause false interrupts to the host.

Workaround:

Use a 34-39 ohm pull-up resistor on the P_INT[D:A]# signals.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

30.

Secondary bus may not initialize correctly at 100 MHz PCI-X or 133 MHz

PCI-X

Problem:

When a 133 MHz PCI-X capable device is plugged into the secondary PCI-X bus supporting

>= 100 MHz PCI-X, the 80331 might not correctly initialize the bus at 100 MHz PCI-X or

133 MHz PCI-X.

Implication:

The bus may initialize at 66 MHz PCI-X.

Workaround:

Replace the 3.3 Kohm pull-up resistor on S_PCIXCAP with a 1.5 Kohm resistor.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

31.

Coalesced writes to 32-bit memory can cause data corruption

Problem:

The Bus Interface Unit (BIU) can cause data corruption within the memory controller unit when

either an 8-byte write with a starting address offset of four (i.e., DWord alignment) or a 12-byte

write is done to 32-bit memory (or the 32-bit memory region).

Implication:

Can cause data corruption. This is not an issue with 64-bit memory subsystems.

Workaround:

When the use of 32-bit memory or the 32-bit memory region is required, write coalescing must be

turned off.

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

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