QG80331M667 datasheet(59/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Specification Clarifications

30.

DMA transactions from local memory to a conventional PCI target can

complete out of order

Issue:

It is possible for the Outbound ATU to get backed up and retry the DMA unit.

When this

occurs, the possibility exists for DMA transactions to complete out of order as each DMA has 3

separate data queues and there is no guarantee as to which one of the queues will drain on the retry.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9

31.

SBR1 Programming with Bank 1 Unpopulated

Issue:

When using single-banked DDR-II DIMMs and the SDRAM Boundary Register 1 (SBR1;

FFFF_E514h) is not programmed to match the SDRAM Boundary Register 0 (SBR0;

FFFF_E510h), the wrong ODT signal will become activated. The memory controller provides two

ODT (On Die Termination) signals (ODT[1:0]) which are used with DDR-II DIMMs to turn on

termination during writes.

Section 8.7.6 in the Intel® 80331 I/O Processor Developer’s Manual (273942) states, “If bank 1 is

unpopulated, SBR1[6:0] is programmed either with all zeroes or a value equal to SBR0[6:0].” To

clarify this statement for single-banked DDR-II DIMMs, if bank 1 is unpopulated, then the entire

SBR1 must be programmed the same as SBR0. This includes lower bits 06:00 and upper bits

31:30. Bits 30:07 are reserved and should not be written. The memory controller compares the

entire range of the SBR0 and SBR1 to determine which ODT signal to enable. If the upper bits

31:30 in SBR0 and SBR1 do not match, then ODT1 will become active instead of ODT0.

In addition, when bank 1 is unpopulated, SBR1[6:0] should never be zero if SBR0[6:0] is non-zero.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

32.

32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit Aligned

Writes

Issue:

In applications that run the PCI bus segment in 32-bit PCI Mode or 64-bit PCI Mode with 32-bit

targets, write transactions that are on unaligned 64-bit addresses are promoted to 64-bit aligned

writes. The first half of the 64-bit write is on a 64-bit aligned address and has the BE# signals

disabled. Therefore, the write is invalid. The second half on the 64-bit write is a valid write with the

BE# enabled and the write is to the intended 32-bit address.

Per the PCI Local Bus Specification, Revision 2.2, PCI compliant devices should ignore the first

half of the 64-bit write due to the BE# signals being disabled.

For devices that support using the I/O window, the 64-bit write does not occur when using the ATU

I/O Window and only the expected 32-bit write occurs.

For memory mapped devices, the only option is to run in PCI-X mode, where the byte count and

starting address are consistent with the actual number of bytes to be written (i.e., 4). When a 64-bit

PCI-X request gets downshifted, the requester can use the starting address/byte count to recognize

that the write request does not cross a DWORD address boundary and only perform a single 32-bit

wide data cycle.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

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