QG80331M667 datasheet(40/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

to ‘1’). The 32-bit address range of FFFF_E000h to FFFF_FFFFh on the internal bus, represents

MMR and reserved space. When a 64-bit address in this range is presented on the internal bus,

multiple internal bus units, one of them being the BIU, will claim the transaction.

Note:

Only the DMA can generate a 64-bit address (DAC) on the internal bus.

Implication:

Using DAC addresses in the xxxx_xxxx_FFFF_E000h to xxxx_xxxx_FFFF_FFFFh range on the

internal bus will cause an internal bus conflict that may result in the reception of undesired data and

setting of error flags.

Workaround:

Avoid

using

the

DMA

with

DAC

addresses

the

xxxx_xxxx_FFFF_E000h

xxxx_xxxx_FFFF_FFFFh range. This can be done by utilizing one of the two 64MB ATU

outbound memory windows (8000 0000H or 8400 0000H) and its corresponding outbound

translation registers (OMWTVR0/OUMWTR0 or OMWTVR1/OUMWTR1) in order to present a

32 bit address on the internal bus and generate a 64 bit address on the PCI bus.

The upper translate value register should be programmed with the upper 32 bits of the desired PCI

address. The lower translate value register would then be configured to OR in the appropriate value

such that the desired lower 32 bits appear on the PCI bus after translation. Refer to Section 3.2.2

“Outbound Transactions – Single Address Cycle (SAC) Internal Bus Transactions” in The Intel®

80331 I/O Processor Developer’s Manual (274065) for more information on how the windowing

and translation scheme works.

It is possible to now generate the 32 bit internal bus transaction either using the core or the DMA.

Both options are viable and one may be preferable over the other depending on the application.

Note:

Use of the DMA to generate the transaction would require not only the modification of the

descriptors in question and setting of the memory-memory transfer enable bit (DCRx) for those

descriptors, but care must also be taken not to allow any individual transfer to overrun the size of

the outbound window (64MB).

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

59.

PCIX-to-PCI Memory Read issued as 32-bit, then retried as 64-bit

Problem:

A 32-bit memory read transaction from PCI-X to PCI may be retried with REQ64# asserted in

violation of the PCI specification.

Implication:

A memory read with multiple dataphases requested is issued from the PCI-X side across the bridge

and played on the PCI-side of the bridge. This read gets some data and is then disconnected by the

target. At the same time, a memory read with starting address less than 4DW from the next ADB is

enqueued on the PCI-X side and then issued on the PCI immediately after the first read is discon-

nected.

This read is issued the first time with REQ64# deasserted and is retried by the target (delayed

transaction). Some time later, the bridge re-issues this read with REQ64# asserted, violating PCI

requirements that REQ64# remain the same for every retry.

Note:

This can only occur in PCI-X to PCI transactions. This behavior is fairly common in many PCI

devices and generally has minimal side effects on overall system performance. In some systems,

depending on the setting of the discard timer, a delay may occur before normal system throughput

is restored.

Workaround:

Limit the PCI-side to 32-bit only in X-to-I configurations.

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

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