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QG80331M667 Arkusz danych(PDF) 15 Page - Intel Corporation

Numer części QG80331M667
Szczegółowy opis  Intel 80331 I/O Processor Specification Update
PDF  67 Pages
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Producent  INTEL [Intel Corporation]
Strona internetowa  http://www.intel.com
Logo INTEL - Intel Corporation

QG80331M667 Arkusz danych(HTML) 15 Page - Intel Corporation

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Specification Update
15
Intel® 80331 I/O Processor
Summary Table of Changes
Specification Clarifications
No.
Steppings
Page
Status
Specification Clarifications
A-1
B-0
C-x
D-0
D-1
1
XXXX
X
51
No Fix
64 MB and 2 GB DDR333 capacities not to be tested in post-silicon
validation
2
XXXX
X
51
No Fix
DDR-II 400 Unbuffered DIMMs are not supported
3
XXXX
X
51
No Fix
Interrupt behavior in the 80331 no bridge mode
4
XXXX
X
51
No Fix
Memory map for 2 GByte of DDR memory
5
XXXX
X
51
No Fix
Back to back MCU MMR reads
6
XXXX
X
52
No Fix
Write requirements for the Peripheral Bus Interface
7
XXXX
X
52
No Fix
PCI-X Status Register during PCI mode
8
XXXX
X
52
No Fix
M_RST# driven to DDR-II or DDR-I voltage levels
9
XXXX
X
52
No Fix
BIU master abort causes two interrupts on reads.
10
XXXX
X
53
No Fix
Reset Internal Bus (PCSR.5) usage
11
XXXX
X
53
No Fix
No Bridge Mode (BRG_EN) validation
12
XXXX
X
53
No Fix
Potential race condition with Interrupt Controller Unit status bits
13
XXXX
X
54
No Fix
Bus Interface Unit follows PCI ordering rules
14
XXXX
X
55
No Fix
UART, I2C and GPIO memory mapped registers should be
addressed with 32-bit accesses
15
XXXX
X
55
No Fix
Flash Wait States
16
XXXX
X
55
No Fix
UART Interrupt Identification Register
17
XXXX
X
55
No Fix
Reads on 16-bit PBI bus operate as 32-bit
18
XXXX
X
56
No Fix
Embedded Design Usage Model - Secondary PCI bus only
19
XXXX
X
56
No Fix
3.3 V to 1.5 V leakage
20
XXXX
X
56
No Fix
Accessing “reserved” registers in “no bridge” mode
21
XXXX
X
56
No Fix
Power plane isolation for Battery Back-Up (BBU) mode
22
XXXX
X
57
No Fix
AAU result can be written directly to PCI host memory
23
XXXX
X
57
No Fix
PWRDELAY functionality during power sequencing
24
XXXX
X
57
No Fix
PBI lockout condition
25
XX
57
No Fix
Interleaving descriptors with D-0 AAU
26
XXXX
X
58
No Fix
RCVDLY setting for DDR-I memory
27
XXXX
X
58
No Fix
ATUBAR3 Functionality
28
XXXX
X
58
No Fix
VREF isolation for Battery Back-up (BBU) mode
29
XXXX
X
58
No Fix
I2C Unit Enabling
30
XXXX
X
59
No Fix
DMA transactions from local memory to a conventional PCI target
can complete out of order
31
XXXX
X
59
No Fix
SBR1 Programming with Bank 1 Unpopulated
32
XXXX
X
59
No Fix
32-bit Writes to Unaligned 64-bit Addresses are Promoted to 64-bit
Aligned Writes
33
XXXX
60
Fixed
Case Temperature Clarification.



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