QG80331M667 datasheet(56/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Specification Clarifications

18.

Embedded Design Usage Model - Secondary PCI bus only

Issue:

The 80331, with bridge enabled, can be used in embedded designs that require central resource

functionality. The secondary PCI bus provides clockouts, arbitration and interrupt inputs for up to

four devices. The ATU can generate configuration cycles to all devices on the secondary PCI bus.

In contrast, the primary PCI bus cannot be used in embedded designs, therefore no PCI devices can

be placed on this bus. The primary PCI bus was designed to be driven by a central resource only.

Clockouts, arbitration and interrupt inputs are not provided on the primary PCI bus. When the ATU

generates configuration cycles they are not forwarded from the secondary PCI bus to the primary

PCI bus. Also, the Intel XScale® core cannot write to the bridge configuration registers.

When using the 80331 in embedded designs, keep the bridge enabled (BRG_EN=1) and connect

the primary PCI bus as follows:

1. P_CLK is still required. Clock frequency should be 66 MHz, since external pull-ups need to be

on P_M66EN, P_DEVSEL#, P_STOP# and P_TRDY#. With these signals pulled high, the

80331 is put into conventional PCI mode expecting a 66 MHz input clock. If providing a

33MHz clock is easier/cheaper, then tie P_M66EN low.

2. P_RST# still required from an external reset source.

3. P_RCOMP needs 100

Ω to ground

4. With P_REQ64# tied high, P_AD[63:32], P_PAR64, and P_C/BE[7:4]# have internal pull-ups

5. Put pull-ups (8.2 K to 3.3V) on all other primary PCI signals.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

19.

3.3 V to 1.5 V leakage

Issue:

There is a leakage path from 3.3 V rail to the 1.5 V rail. When the 3.3 V is powered on and the

1.5 V is not, then ~500 mV is seen on the 1.5 V rail. This leakage is expected and does not cause

any long-term reliability issues.

For related issues, see Documentation Change 10 (“Power sequence timing” on page 66) and

Non-Core Errata 50 (“Secondary bus PCI RST# pulse prior to the rising edge of P_RST#” on

page 36).

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

20.

Accessing “reserved” registers in “no bridge” mode

Issue:

In general, accessing “reserved” registers or bit fields must never be done, as these “reserved”

fields might be used for test information or might be implemented in future product revisions.

Specifically, accessing peripheral memory mapped registers at FFFF_F5D0h to FFFF_F5DFh

when in “no bridge” mode, causes the 80331 to hang. Do not access these registers.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

21.

Power plane isolation for Battery Back-Up (BBU) mode

Issue:

During battery back-up (BBU) mode, when the battery powers the DIMM and the VCC25/18

signals (1.8 V or 2.5 V, depending on the memory type being used) on a single power plane, the

battery life is probably reduced, due to leakage.

To attain longer battery life, the DIMM and VCC25/18 power planes must be isolated. The

power-plane isolation can be accomplished by using a FET.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

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