QG80331M667 datasheet(31/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

40.

PCI-X to PCI Memory Read double-word near 1MB boundary may cause the

system to hang

Problem:

PCI-X to PCI Memory Read DWORD near a 1 MB boundary may cause the system to hang.

Implication:

In the following scenario:

• A master on the PCI-X bus initiates a Memory Read DWORD through the bridge, with a

starting address that is not DW aligned and is within the last 4 bytes of a 1 MB address

boundary.

• On the PCI side, the bridge initiates the request and disconnects after a single data phase. The

transaction should end at this point, but instead, the transaction is then issued a second time

with the starting address at the 1 MB boundary before being retired.

• Back on the PCI-X side, the completion is issued with the correct data for the initial 4-byte

request, followed by a second “unexpected” completion. As a result of the second completion,

the internal resource counter gets decremented twice, causing the resource checking logic to

assume there is no more room on the chip for split transactions.

• At this point the bridge can no longer process upstream non-posted requests and terminates

them with retry.

Note:

The above failure only occurs on a Memory Read DWORD from PCI-X to PCI when the starting

address is not DW aligned. A Memory Read DWORD to 0xffffc does not fail, whereas a read to

0xfffff does fail.

Workaround:

This issue only affects PCI-X to PCI transactions. PCI to PCI-X, PCI to PCI and PCI-X to PCI-X

transactions are not affected. PCI-X to PCI implementations should not attempt to do a Memory

Read DWORD that is not DW aligned and is within the last 4 bytes of a 1 MB address boundary.

Status:

Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.

41.

PCI-X to PCI Memory Read Block across 1MB boundary may cause data

corruption

Problem:

PCI-X to PCI Memory Read Block across 1MB boundary may cause data corruption.

Implication:

In the following scenario:

• A master on the PCI-X bus initiates a Memory Read Block through the bridge, with a starting

address + byte count that crosses a 1 MB boundary. The request is not DWORD aligned and

starts less than three data phases from the 1 MB boundary.

• On the PCI side, the bridge initiates the request by setting the low two address bits to 00b as

required by the PCI Local Bus Specification, Revision 2.3.

• The bridge receives data up to the boundary and disconnects, then requests the remainder of

the data in a second transaction.

• On the source bus, the bridge should deliver a small completion up to the 1MB boundary with

the BCM bit set. However, in this case the bridge plays the request without BCM and uses the

full remaining byte count. Since the bridge can not disconnect, it winds up satisfying the byte

count with garbage for data after the boundary.

Note:

For failure to occur, starting address and byte count must be set so the request crosses the 1 MB

boundary, but bytes requested after the boundary are less than 4 bytes. Requests that are DWORD

aligned do not fail, nor do requests that do not cross the 1MB boundary (even when not aligned).

Workaround:

This issue only affects PCI-X to PCI transactions. PCI to PCI-X, PCI to PCI and PCI-X to PCI-X

transactions are not affected. PCI-X to PCI implementations that do not cross a 1 MB boundary

does not experience this issue.

Status:

Fixed. Fixed in C-0 stepping. See the Table , “Summary Table of Changes” on page 9.

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