QG80331M667 datasheet(22/67 Pages) INTEL

22 / 67 page

Specification Update

Intel® 80331 I/O Processor

Non-Core Errata

14.

SDCR0.2 implemented as ‘Reserved’

Problem:

The attribute for bit 2 in the MCU SDRAM Control Register 0 (SDCR0) is incorrectly

implemented as ‘Reserved’, instead of ‘Read Only’. Since it is ‘reserved’, software cannot rely on

reading this bit to determine when DDR or DDR-II memory type is selected. The external state of

MEM_TYPE can not be correctly identified by reading this bit.

Implication:

This bit cannot be used to determine memory type.

Workaround:

Since hardware design is specific to either DDR or DDR-II, software engineers know what

memory is being used in their application and therefore need not rely on this bit. Also, software can

read DIMM information via Serial Presence Detect (SPD).

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

15.

32-bit region missing proper address decode

Problem:

When connected to 64-bit SDRAM, a 32-bit region can be defined by the S32SR register. There is an

issue with the calculation that is performed to determine whether a transaction is in the 32-bit window

or not. The MCU address decoder is missing the MSB for the 32-bit region hit/miss. This issue only

applies to systems that intend to use the 32-bit region. There are no other base address restrictions.

Implication:

32-bit addresses can be decoded improperly causing unstable code execution.

Workaround:

Do not allow the base address, defined by SDBR, to be aligned on an odd 1G boundary (e.g., bit 30

cannot be set to a ‘1’:

For example, allowable base addresses: 0x8000_0000, 0xA000_0000, 0x2000_0000

Non-allowable base addresses: 0x4000_0000, 0xC000_0000, 0x4100_0000

Status:

Fixed. Fixed in B-0. See the Table , “Summary Table of Changes” on page 9.

16.

S_GNT[3:2]# outputs are not pulled high when Bridge is disabled.

Problem:

When the bridge is disabled (BRG_EN = 0), the S_GNT[3:2]# signals float (Z). These signals need

to not float, but be pulled high (H).

Implication:

No negative impact expected.

Workaround:

External pull-ups are required.

Status:

Fixed. Fixed in B-0 stepping. See the Table , “Summary Table of Changes” on page 9.

17.

Split Transaction Commitment limit register mechanism, in the PCI-X

bridge, does not operate as implied by the PCI-X Addendum to the PCI

Local Bus Specification, Revision 1.0a

Problem:

The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a requires that the bridge

operate in a fully buffered mode. The 80331 bridge allows software to write the Split Transaction

limit register, to allow compatibility with existing software, however, it behaves as though the

regard to the sequence size or the amount of available buffer space.

Implication:

This behavior could result in the bridge split completion buffers becoming full, while additional

split completions are being received. When this situation occurs, the bridge either issues a retry or

disconnects on the next ADB, until buffer space is available.

Workaround:

No workaround.

Status:

No Fix. Not to be fixed. See the Table , “Summary Table of Changes” on page 9.

QG80331M667 Arkusz danych(PDF) 22 Page - Intel Corporation

QG80331M667 Arkusz danych(HTML) 22 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Arkusz danych Pobierz

Link URL