QG80331M667 datasheet(58/67 Pages) INTEL

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Specification Update

Intel® 80331 I/O Processor

Specification Clarifications

Therefore if enabled, all descriptors are processed as P+Q descriptor formats.

If disabled, all descriptors are processed as prior AAU definitions (ie - straight XOR).

In order to mix RAID-5 with P+Q RAID-6, enable P+Q RAID-6 GF Multiply for the AAU, and

build all RAID-5 XOR descriptors as P+Q RAID-6 descriptors, where the GF Multiplier Byte

values are all 0x01.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

26.

RCVDLY setting for DDR-I memory

Issue:

The Receive Enable Delay Register (RCVDLY at FFFF_F550h) is used for DQS receive enable

calibration. In other words, RCVDLY adjusts the memory controllers relationship of DQS to an

internal M_CLK.

The RCVDLY value is highly dependant on the board layout and DIMM characteristics. Also, the

memory controller only supports a non integer CAS latency (tCAS = 2.5, SDCR0.9:8) for DDR-I,

which means that RCVDLY may need to be adjusted because DQS is no longer synchronized with

M_CLK.

Therefore, when using DDR-I memory, the RCVDLY default setting of 5 may need to be changed

to 6 or 7 to operate correctly with a specific DIMM based on the board layout. For example, the

Redboot reference code provided by Intel uses a value to 7 to allow for a wider compatibility with

various DIMMs.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

27.

ATUBAR3 Functionality

Issue:

The private memory window of the secondary PCI segment defines an address range that the

80331 uses to map private devices to, and to locate local memory for private device access. This

range is intended to be mapped to the ATUs private BAR window (ATUBAR3) and the private

device BARs. Note that even when the private addressing is enabled, the normal 80331 behavior

defined for BME, MSE, IOSE bits in the ATUCMD register are still true. Therefore, when the ATU

Memory Space Enable bit is cleared, all ATU BARs including ATUBAR3 will be unable to claim

any memory transactions. For example, this bit is typically cleared during a PCI bus scan /

enumeration.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

28.

VREF isolation for Battery Back-up (BBU) mode

Issue:

During battery back-up (BBU) mode, the DIMM power can be isolated from the 80331 IOP power.

This isolation should also include the VREF signal for the DIMM interface. Due to leakage, the

VREF signal for the DIMM should be isolated from the VREF signal for the IOP. This is to ensure

that VREF for the DIMM is not disturbed as the IOP powers down when entering battery back-up

(BBU) mode. The isolation can be provided by using separate voltage dividers or a FET.

For related issues, refer to Specification Clarification 21, “Power plane isolation for Battery

Back-Up (BBU) mode” on page 56.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9.

29.

I2C Unit Enabling

Issue:

Software must guarantee that the I2C bus is idle before enabling the I2C unit. Failure to do so could

result in unstable behavior. The IBMR register can be used to monitor the state of the SCL and

SDA pins in order to determine bus activity. The I2C Bus Busy bit in the I2C Status Register

(ISR.3) can not be used for this purpose, as it is only valid when the I2C unit is enabled.

Status:

No Fix. See the Table , “Summary Table of Changes” on page 9

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